5 files changed, 92 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index 5fe073a590..acd2c45417 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -1,3 +1,5 @@
+subdirs-y += sdram_params/
+
 bootblock-y += boardid.c
 bootblock-y += bootblock.c
 bootblock-y += chromeos.c
@@ -12,6 +14,7 @@ romstage-y += boardid.c
 romstage-y += chromeos.c
 romstage-y += memlayout.ld
 romstage-y += romstage.c
+romstage-y += sdram_configs.c
 
 ramstage-y += boardid.c
 ramstage-y += chromeos.c
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 4855334149..629692dd72 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -14,11 +14,13 @@
  */
 
 #include <arch/stages.h>
+#include <soc/emi.h>
 #include <soc/mmu_operations.h>
 #include <soc/mt6358.h>
 
 void platform_romstage_main(void)
 {
 	mt6358_init();
+	mt_mem_init(get_sdram_config());
 	mtk_mmu_after_dram();
 }
diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c
new file mode 100644
index 0000000000..25bbe8ffe2
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_configs.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boardid.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/emi.h>
+
+static const char *const sdram_configs[] = {
+	[1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB",
+};
+
+static struct sdram_params params;
+
+const struct sdram_params *get_sdram_config(void)
+{
+	uint32_t ramcode = ram_code();
+
+	if (ramcode >= ARRAY_SIZE(sdram_configs) ||
+	    cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params),
+				CBFS_TYPE_STRUCT) != sizeof(params))
+		die("Cannot load SDRAM parameter file!");
+
+	return &params;
+}
diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc
new file mode 100644
index 0000000000..d15c40dd03
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc
@@ -0,0 +1,9 @@
+sdram-params :=
+sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB
+
+$(foreach params,$(sdram-params), \
+	$(eval cbfs-files-y += $(params)) \
+	$(eval $(params)-file := $(params).c:struct) \
+	$(eval $(params)-type := struct) \
+	$(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \
+)
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c
new file mode 100644
index 0000000000..da6c7d255e
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/emi.h>
+
+struct sdram_params params = {
+	.impedance = {
+		[ODT_OFF] = {0x7, 0x6, 0x0, 0xF},
+		[ODT_ON] = {0x9, 0x9, 0x0, 0xF}
+	},
+	.wr_level = {
+		[CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} },
+		[CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} }
+	},
+	.cbt_cs = {
+		[CHANNEL_A] = {0x0, 0x0},
+		[CHANNEL_B] = {0x0, 0x0}
+	},
+	.cbt_mr12 = {
+		[CHANNEL_A] = {0x52, 0x52},
+		[CHANNEL_B] = {0x52, 0x52}
+	},
+	.emi_cona_val = 0xF053F154,
+	.emi_conh_val = 0x44440003,
+	.emi_conf_val = 0x00421000,
+	.chn_emi_cona_val = {0x0444F051, 0x0444F051},
+	.cbt_mode_extern = CBT_NORMAL_MODE,
+	.delay_cell_unit = 868,
+};