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-rw-r--r--src/soc/amd/cezanne/bootblock.c6
-rw-r--r--src/soc/amd/cezanne/early_fch.c9
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h1
3 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index c3cb138473..fc1c5e7c0a 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -92,6 +92,12 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
set_caching();
write_resume_eip();
enable_pci_mmconf();
+ /*
+ * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h
+ * routing as early as possible
+ */
+ if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
+ configure_port80_routing_early();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index fdfa17aad3..d76afc8174 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -32,6 +32,13 @@ static void reset_i2c_peripherals(void)
sb_reset_i2c_peripherals(&reset_info);
}
+/* Initialize port80h routing early if needed */
+void configure_port80_routing_early(void)
+{
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+ espi_setup();
+}
+
/* Before console init */
void fch_pre_init(void)
{
@@ -69,6 +76,6 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
espi_setup();
}
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 0ed5f33f22..386d3c1e87 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -105,6 +105,7 @@
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
+void configure_port80_routing_early(void);
void fch_pre_init(void);
void fch_early_init(void);
void fch_init(void *chip_info);