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-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S4
3 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 3183cc6e06..837394c8c9 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -132,10 +132,6 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
- */
movl $_program, %eax
andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 259e321c38..71e344778f 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -121,10 +121,6 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
- */
movl $_program, %eax
andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 806102f0b0..4e36538414 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -322,10 +322,6 @@ cache_rom:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
- */
movl $_program, %eax
andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax