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-rw-r--r--src/arch/arm/armv7/mmu.c4
-rw-r--r--src/arch/x86/failover.ld6
-rw-r--r--src/arch/x86/memlayout.ld2
-rw-r--r--src/commonlib/storage/sdhci.c6
-rw-r--r--src/cpu/amd/family_10h-family_15h/fidvid.c2
-rw-r--r--src/cpu/amd/quadcore/amd_sibling.c2
-rw-r--r--src/cpu/intel/hyperthreading/intel_sibling.c2
-rw-r--r--src/device/device.c4
-rw-r--r--src/drivers/intel/wifi/wifi.c4
-rw-r--r--src/drivers/pc80/pc/keyboard.c2
-rw-r--r--src/include/device/hypertransport_def.h2
-rw-r--r--src/include/device/i2c_simple.h2
-rw-r--r--src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c2
-rw-r--r--src/mainboard/amd/olivehillplus/BiosCallOuts.c2
-rw-r--r--src/mainboard/amd/torpedo/gpio.c14
-rw-r--r--src/mainboard/bap/ode_e21XX/BiosCallOuts.c2
-rw-r--r--src/mainboard/pcengines/apu1/mainboard.c12
-rw-r--r--src/mainboard/pcengines/apu2/BiosCallOuts.c2
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c4
-rw-r--r--src/northbridge/amd/pi/agesawrapper.c2
-rw-r--r--src/northbridge/intel/i945/gma.c4
-rw-r--r--src/northbridge/intel/i945/raminit.c2
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c2
-rw-r--r--src/soc/amd/common/block/pi/agesawrapper.c2
-rw-r--r--src/soc/nvidia/tegra124/bootblock.c2
-rw-r--r--src/soc/nvidia/tegra210/bootblock.c2
-rw-r--r--src/southbridge/amd/cimx/sb800/cfg.c2
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/nvidia/ck804/ck804.h2
31 files changed, 51 insertions, 51 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 14f5f7ade9..ce9d3fd9d8 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -277,7 +277,7 @@ void mmu_init(void)
for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES)
table[0] = ATTR_UNUSED;
- if (CONFIG_ARM_LPAE) {
+ if (CONFIG(ARM_LPAE)) {
pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
pte_t *pmd = ttb_buff;
int i;
@@ -331,7 +331,7 @@ void mmu_init(void)
* See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
*/
write_ttbcr(
- CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */
+ CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */
0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */
);
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
index b32aa29bef..a9a5942a2f 100644
--- a/src/arch/x86/failover.ld
+++ b/src/arch/x86/failover.ld
@@ -28,7 +28,7 @@ SECTIONS
* boundary anyway, so no pad byte appears between _rom and _start.
*/
.bogus ROMLOC_MIN : {
- . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
+ . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4);
ROMLOC = .;
} >rom = 0xff
@@ -50,10 +50,10 @@ SECTIONS
* address gets applied.
*/
ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
+ (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
/* Post-check proper SIPI vector. */
- _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff),
+ _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff),
"Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : {
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 8e073f25cf..cc72552254 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -26,7 +26,7 @@ SECTIONS
* conditionalize with macros.
*/
#if ENV_RAMSTAGE
- RAMSTAGE(CONFIG_RAMBASE, (CONFIG_RELOCATABLE_RAMSTAGE ? 8M :
+ RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M :
CONFIG_RAMTOP - CONFIG_RAMBASE))
#elif ENV_ROMSTAGE
diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c
index 1370a91a14..5c85e99655 100644
--- a/src/commonlib/storage/sdhci.c
+++ b/src/commonlib/storage/sdhci.c
@@ -30,9 +30,9 @@
#include <timer.h>
#include <commonlib/stdlib.h>
-#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \
- || (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \
- || (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \
+#define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
+ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \
+ || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \
|| ENV_POSTCAR || ENV_RAMSTAGE)
__weak void *dma_malloc(size_t length_in_bytes)
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index db58f5dd34..579cae5d1d 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -1084,7 +1084,7 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
- for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv);
+ for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv);
#endif
print_debug_fv("common_fid = ", fv.common_fid);
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index 000cb88307..f9aba5181c 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -74,7 +74,7 @@ u32 get_apicid_base(u32 ioapic_num)
u32 siblings;
u32 nb_cfg_54;
- u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
+ u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
get_option(&disable_siblings, "multi_core");
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index f2f28f6377..e634f85fc3 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -24,7 +24,7 @@
#endif
static int first_time = 1;
-static int disable_siblings = !CONFIG_LOGICAL_CPUS;
+static int disable_siblings = !CONFIG(LOGICAL_CPUS);
/* Return true if running thread does not have the smallest lapic ID
* within a CPU core.
diff --git a/src/device/device.c b/src/device/device.c
index ae0dbdb1d7..1b4255bffe 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -790,12 +790,12 @@ static void set_vga_bridge_bits(void)
if (!vga)
vga = vga_onboard;
- if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard)
+ if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && vga_onboard)
vga = vga_onboard;
/* If we prefer plugin VGA over chipset VGA, the chipset might
want to know. */
- if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) &&
+ if (!CONFIG(ONBOARD_VGA_IS_PRIMARY) && (vga != vga_onboard) &&
vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) {
printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n");
vga_onboard->ops->disable(vga_onboard);
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index d78b0076fa..c0f665f6bb 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -101,7 +101,7 @@ static void emit_sar_acpi_structures(void)
package_size = 1 + 1 + BYTES_PER_SAR_LIMIT;
acpigen_write_package(package_size);
acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI);
- acpigen_write_dword(CONFIG_SAR_ENABLE);
+ acpigen_write_dword(CONFIG(SAR_ENABLE));
for (i = 0; i < BYTES_PER_SAR_LIMIT; i++)
acpigen_write_byte(sar_limits.sar_limit[0][i]);
acpigen_pop_len();
@@ -130,7 +130,7 @@ static void emit_sar_acpi_structures(void)
package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT;
acpigen_write_package(package_size);
acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI);
- acpigen_write_dword(CONFIG_DSAR_ENABLE);
+ acpigen_write_dword(CONFIG(DSAR_ENABLE));
acpigen_write_dword(CONFIG_DSAR_SET_NUM);
for (i = 1; i < NUM_SAR_LIMITS; i++)
for (j = 0; j < BYTES_PER_SAR_LIMIT; j++)
diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c
index 3849e73df0..bfd05c19d1 100644
--- a/src/drivers/pc80/pc/keyboard.c
+++ b/src/drivers/pc80/pc/keyboard.c
@@ -249,7 +249,7 @@ uint8_t pc_keyboard_init(uint8_t probe_aux)
enum cb_err err;
uint8_t aux_dev_detected;
- if (!CONFIG_DRIVERS_PS2_KEYBOARD)
+ if (!CONFIG(DRIVERS_PS2_KEYBOARD))
return 0;
if (acpi_is_wakeup_s3())
diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h
index 4b340e862e..ef9de2c3aa 100644
--- a/src/include/device/hypertransport_def.h
+++ b/src/include/device/hypertransport_def.h
@@ -23,7 +23,7 @@ static inline bool offset_unit_id(bool is_sb_ht_chain)
{
bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
|| (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
- return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ return need_offset && (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY)
|| is_sb_ht_chain);
}
diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h
index dcde601994..e3cc8921fd 100644
--- a/src/include/device/i2c_simple.h
+++ b/src/include/device/i2c_simple.h
@@ -54,7 +54,7 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data,
static inline int i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int count)
{
- if (CONFIG_SOFTWARE_I2C)
+ if (CONFIG(SOFTWARE_I2C))
if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus])
return software_i2c_transfer(bus, segments, count);
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index c6e575d9ee..af5d34e613 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -269,7 +269,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index a6f4267649..e3107b18a5 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -253,7 +253,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
- FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 4a8861cd33..51e35713ea 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -340,7 +340,7 @@ void gpioEarlyInit(void) {
//
// Enable/Disable OnBoard LAN
//
- if (!CONFIG_ONBOARD_LAN)
+ if (!CONFIG(ONBOARD_LAN))
{ // 1 - DISABLED
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
@@ -358,7 +358,7 @@ void gpioEarlyInit(void) {
//
// Enable/Disable 1394
//
- if (!CONFIG_ONBOARD_1394)
+ if (!CONFIG(ONBOARD_1394))
{ // 1 - DISABLED
// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
@@ -387,7 +387,7 @@ void gpioEarlyInit(void) {
// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
// disable Onboard NEC USB3.0 controller
- if (!CONFIG_ONBOARD_USB30) {
+ if (!CONFIG(ONBOARD_USB30)) {
RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
@@ -401,7 +401,7 @@ void gpioEarlyInit(void) {
// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO07: BT_ON, 0 - OFF, 1 - ON
//
- if (!CONFIG_ONBOARD_BLUETOOTH) {
+ if (!CONFIG(ONBOARD_BLUETOOTH)) {
//- if (SystemConfiguration.amdBlueTooth == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
//- }
@@ -412,7 +412,7 @@ void gpioEarlyInit(void) {
// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
//
- if (!CONFIG_ONBOARD_WEBCAM) {
+ if (!CONFIG(ONBOARD_WEBCAM)) {
//- if (SystemConfiguration.amdWebCam == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
//- }
@@ -423,7 +423,7 @@ void gpioEarlyInit(void) {
// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
//
- if (!CONFIG_ONBOARD_TRAVIS) {
+ if (!CONFIG(ONBOARD_TRAVIS)) {
//- if (SystemConfiguration.amdTravisCtrl == 0) {
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
//- }
@@ -432,7 +432,7 @@ void gpioEarlyInit(void) {
//
// Disable Light Sensor if needed
//
- if (CONFIG_ONBOARD_LIGHTSENSOR) {
+ if (CONFIG(ONBOARD_LIGHTSENSOR)) {
//- if (SystemConfiguration.amdLightSensor == 1) {
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
//- }
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
index 362b5ba616..1d86d53be9 100644
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
@@ -255,7 +255,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
- FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 79a54b51eb..e5e30e031c 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -139,16 +139,16 @@ static void config_gpio_mux(void)
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
if (uart)
- uart->enabled = CONFIG_APU1_PINMUX_UART_C;
+ uart->enabled = CONFIG(APU1_PINMUX_UART_C);
if (gpio)
- gpio->enabled = CONFIG_APU1_PINMUX_GPIO0;
+ gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
if (uart)
- uart->enabled = CONFIG_APU1_PINMUX_UART_D;
+ uart->enabled = CONFIG(APU1_PINMUX_UART_D);
if (gpio)
- gpio->enabled = CONFIG_APU1_PINMUX_GPIO1;
+ gpio->enabled = CONFIG(APU1_PINMUX_GPIO1);
}
static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
@@ -165,11 +165,11 @@ static void config_addon_uart(void)
struct device *uart;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
- if (uart && uart->enabled && CONFIG_UART_C_RS485)
+ if (uart && uart->enabled && CONFIG(UART_C_RS485))
pnp_raw_resource(uart, 0xf2, 0x12);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
- if (uart && uart->enabled && CONFIG_UART_D_RS485)
+ if (uart && uart->enabled && CONFIG(UART_D_RS485))
pnp_raw_resource(uart, 0xf2, 0x12);
}
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 8fc3d5a9ff..535024a86f 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -69,7 +69,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
- FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 16b7becccc..1d071c1877 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -177,7 +177,7 @@ static void ht_route_link(struct bus *link, scan_state mode)
pci_write_config32(link->dev, link->cap + 0x14, busses);
if (mode == HT_ROUTE_FINAL) {
- if (CONFIG_HT_CHAIN_DISTRIBUTE)
+ if (CONFIG(HT_CHAIN_DISTRIBUTE))
parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1;
else
parent->subordinate = link->subordinate;
@@ -1450,7 +1450,7 @@ static void cpu_bus_scan(struct device *dev)
siblings = 3; //quad core
}
- disable_siblings = !CONFIG_LOGICAL_CPUS;
+ disable_siblings = !CONFIG(LOGICAL_CPUS);
#if CONFIG(LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core");
#endif
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 28f2876e95..1cc7b7c3d7 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -127,7 +127,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow
// the compiler to flag the error if CONFIG_GFXUMA is not set.
- PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
+ PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (UINT16)
(CONFIG_BOTTOMIO_POSITION >> 24);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index ee656de66a..9c4f410d02 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -677,10 +677,10 @@ static void gma_ngi(struct device *const dev)
if (err == 0)
gfx_set_init_done(1);
/* Linux relies on VBT for panel info. */
- if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA");
}
- if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G");
}
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 05b577787d..be3d17a2fd 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -284,7 +284,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
/* clear self refresh status if check is disabled or not a resume */
- if (!CONFIG_CHECK_SLFRCS_ON_RESUME
+ if (!CONFIG(CHECK_SLFRCS_ON_RESUME)
|| sysinfo->boot_path != BOOT_PATH_RESUME) {
MCHBAR8(SLFRCS) |= 3;
} else {
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index b49165cb3f..7465080bbf 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -67,7 +67,7 @@ void mainboard_romstage_entry(unsigned long bist)
mainboard_config_superio();
/* USB is initialized in MRC if MRC is used. */
- if (CONFIG_USE_NATIVE_RAMINIT) {
+ if (CONFIG(USE_NATIVE_RAMINIT)) {
early_usb_init(mainboard_usb_ports);
}
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index 485dfd719f..5295567a0e 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -180,7 +180,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct);
- PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
+ PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (uint16_t)
(CONFIG_BOTTOMIO_POSITION >> 24);
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 182fadb6d4..c7503041b4 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -64,7 +64,7 @@ void main(void)
pinmux_set_config(PINMUX_UART2_RTS_N_INDEX,
PINMUX_UART2_RTS_N_FUNC_UB3);
- if (CONFIG_BOOTBLOCK_CONSOLE) {
+ if (CONFIG(BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
}
diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c
index 97ea1c9b08..96fb9b22d5 100644
--- a/src/soc/nvidia/tegra210/bootblock.c
+++ b/src/soc/nvidia/tegra210/bootblock.c
@@ -177,7 +177,7 @@ void main(void)
bootblock_mainboard_early_init();
- if (CONFIG_BOOTBLOCK_CONSOLE) {
+ if (CONFIG(BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
printk(BIOS_INFO, "T210: Bootblock here\n");
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 4487df3787..b52918d303 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
#endif
/* LPC */
/* SuperIO hardware monitor register access */
- sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
+ sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/*
* GPP. default configure only enable port0 with 4 lanes,
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 1109290bc7..5ebe47e5fb 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -40,7 +40,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
- if (!CONFIG_PCIB_ENABLE) {
+ if (!CONFIG(PCIB_ENABLE)) {
data |= BIT0;
}
outb(data, 0xCD7);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index eda16da6f7..e9e49649f2 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -418,7 +418,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
- if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
+ if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index fe1d84a2b7..f4464f3b4d 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -433,7 +433,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
- if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
+ if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index fc99d9a848..5505691d1c 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -24,7 +24,7 @@
#endif
#define CK804B_BUSN 0x80
-#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1)
+#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
#ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 09:29:26 +0000