diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/prodrive/atlas/romstage_fsp_params.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index 5c523c5cdc..fedb298ee4 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -60,4 +60,30 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0; memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0; memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; + + // shared clock + memupd->FspmConfig.PcieClkSrcUsage[0] = 0x80; + memupd->FspmConfig.PcieClkSrcClkReq[0] = 0xFF; + // i225 + memupd->FspmConfig.PcieClkSrcUsage[1] = 9; // RP 10 + memupd->FspmConfig.PcieClkSrcClkReq[1] = 1; + + // FIX Apparently Rootports don't like the idea of not having a clksrc and clkreq + // attached to it. For example if we set PcieClkSrcClkReq[1] above to 0xFF (unused) + // it will not come back out of L1. You can easily test this on windows by trying to + // update the i225 driver in device manager or use setpci in Linux to set Device in D3. + // The same applies to all other rootports no matter which devices are connected to it. + // Therefore we put each rootport (that does not have a clkreq, clksrc) + // to a not connected (not routed out) clksrc and clkreq. That seems to be a current FSP Bug. + // workaround and will be removed as soon as FSP is fixed. + memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // Rootport 5 + memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; + memupd->FspmConfig.PcieClkSrcUsage[3] = 5; // Rootport 6 + memupd->FspmConfig.PcieClkSrcClkReq[3] = 0; + memupd->FspmConfig.PcieClkSrcUsage[4] = 8; // Rootport 9 + memupd->FspmConfig.PcieClkSrcClkReq[4] = 0; + memupd->FspmConfig.PcieClkSrcUsage[5] = 6; // Rootport 7 + memupd->FspmConfig.PcieClkSrcClkReq[5] = 0; + memupd->FspmConfig.PcieClkSrcUsage[6] = 7; // Rootport 8 + memupd->FspmConfig.PcieClkSrcClkReq[6] = 0; } |