4 files changed, 13 insertions, 37 deletions
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 8e49a669eb..66451ad711 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -27,6 +27,19 @@ static inline tsc_t rdtsc(void)
 }
 
 #if !defined(__ROMCC__)
+/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
+ * This code is used to prevent use of libgcc's umoddi3.
+ */
+static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
+{
+	tsc->lo = (a & 0xffff) * (b & 0xffff);
+	tsc->hi = ((tsc->lo >> 16)
+		+ ((a & 0xffff) * (b >> 16))
+		+ ((b & 0xffff) * (a >> 16)));
+	tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
+	tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
+}
+
 /* Too many registers for ROMCC */
 static inline unsigned long long rdtscll(void)
 {
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
index 9f49c6ed1b..a861e250c2 100644
--- a/src/northbridge/intel/gm45/delay.c
+++ b/src/northbridge/intel/gm45/delay.c
@@ -2,7 +2,6 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2008 coresystems GmbH
- *               2012 secunet Security Networks AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,17 +23,6 @@
 #include <cpu/intel/speedstep.h>
 #include "delay.h"
 
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
-static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
-{
-	tsc->lo = (a & 0xffff) * (b & 0xffff);
-	tsc->hi = ((tsc->lo >> 16)
-		   + ((a & 0xffff) * (b >> 16))
-		   + ((b & 0xffff) * (a >> 16)));
-	tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
-	tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
-}
-
 /**
  * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
  */
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 780c73050e..3d5d6c6d9c 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -2,7 +2,6 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2008 coresystems GmbH
- *               2012 secunet Security Networks AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,17 +23,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
 
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
-static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
-{
-	tsc->lo = (a & 0xffff) * (b & 0xffff);
-	tsc->hi = ((tsc->lo >> 16)
-		   + ((a & 0xffff) * (b >> 16))
-		   + ((b & 0xffff) * (a >> 16)));
-	tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
-	tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
-}
-
 /**
  * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
  */
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index 01d7abd74c..449b0b99a8 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -26,19 +26,6 @@
  * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
  */
 
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
- * This code is used to prevent use of libgcc's umoddi3.
- */
-static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
-{
-	tsc->lo = (a & 0xffff) * (b & 0xffff);
-	tsc->hi = ((tsc->lo >> 16)
-		+ ((a & 0xffff) * (b >> 16))
-		+ ((b & 0xffff) * (a >> 16)));
-	tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
-	tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
-}
-
 void udelay(u32 us)
 {
 	u32 dword;