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-rw-r--r--src/soc/amd/cezanne/acpi.c10
-rw-r--r--src/soc/amd/common/block/acpi/cpu_power_state.c9
-rw-r--r--src/soc/amd/common/block/include/amdblocks/cpu.h7
-rw-r--r--src/soc/amd/glinda/acpi.c10
-rw-r--r--src/soc/amd/mendocino/acpi.c10
-rw-r--r--src/soc/amd/phoenix/acpi.c10
-rw-r--r--src/soc/amd/picasso/acpi.c10
7 files changed, 17 insertions, 49 deletions
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 8e718ef7b3..de3f46eab2 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -95,13 +95,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
@@ -135,12 +132,9 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
return core_freq;
}
-uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
{
uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core voltage ID */
core_vid = pstate_reg.cpu_vid_0_7;
diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c
index 617c399553..811bea09b2 100644
--- a/src/soc/amd/common/block/acpi/cpu_power_state.c
+++ b/src/soc/amd/common/block/acpi/cpu_power_state.c
@@ -16,7 +16,6 @@
static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
- msr_t pstate_def;
union pstate_msr pstate_reg;
size_t pstate_count, pstate;
uint32_t max_pstate;
@@ -25,15 +24,13 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) {
- pstate_def = rdmsr(PSTATE_MSR(pstate));
-
- pstate_reg.raw = pstate_def.raw;
+ pstate_reg.raw = rdmsr(PSTATE_MSR(pstate)).raw;
if (!pstate_reg.pstate_en)
continue;
- pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
- pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
+ pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_reg);
+ pstate_values[pstate_count].power = get_pstate_core_power(pstate_reg);
pstate_values[pstate_count].transition_latency = 0;
pstate_values[pstate_count].bus_master_latency = 0;
pstate_values[pstate_count].control_value = pstate;
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 76d0326725..3501b22104 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -4,7 +4,6 @@
#define AMD_BLOCK_CPU_H
#include <acpi/acpi.h>
-#include <cpu/x86/msr.h>
#include <types.h>
#define MAX_CSTATE_COUNT 8
@@ -15,8 +14,10 @@ unsigned int get_threads_per_core(void);
void set_cstate_io_addr(void);
void write_resume_eip(void);
-uint32_t get_pstate_core_freq(msr_t pstate_def);
-uint32_t get_pstate_core_power(msr_t pstate_def);
+union pstate_msr; /* proper definition is in soc/msr.h */
+
+uint32_t get_pstate_core_freq(union pstate_msr pstate_reg);
+uint32_t get_pstate_core_power(union pstate_msr pstate_reg);
const acpi_cstate_t *get_cstate_config_data(size_t *size);
#endif /* AMD_BLOCK_CPU_H */
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index b6830a48aa..ce0c7e6001 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -98,12 +98,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq_mul;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_11;
@@ -112,12 +109,9 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
return PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul;
}
-uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
{
uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core voltage ID */
core_vid = pstate_reg.cpu_vid_0_7 | pstate_reg.cpu_vid_8 << 8;
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index f69434f98f..3b557806cc 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -97,13 +97,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
@@ -137,12 +134,9 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
return core_freq;
}
-uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
{
uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core voltage ID */
core_vid = pstate_reg.cpu_vid_0_7;
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index ac21851cfa..1be00f9828 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -98,13 +98,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
@@ -138,12 +135,9 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
return core_freq;
}
-uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
{
uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core voltage ID */
core_vid = pstate_reg.cpu_vid_0_7 | pstate_reg.cpu_vid_8 << 8;
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index faff625fd4..1c6456e1f0 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -99,13 +99,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
@@ -139,12 +136,9 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
return core_freq;
}
-uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
{
uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
- union pstate_msr pstate_reg;
-
- pstate_reg.raw = pstate_def.raw;
/* Core voltage ID */
core_vid = pstate_reg.cpu_vid_0_7;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 07:24:00 +0000