7 files changed, 122 insertions, 19 deletions
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index caf860e6b6..f1be0345e4 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -481,7 +481,8 @@ u8 acpi_slp_type = 0;
 
 static int acpi_is_wakeup(void)
 {
-	return (acpi_slp_type == 3);
+	/* Both resume from S2 and resume from S3 restart at CPU reset */
+	return (acpi_slp_type == 3 || acpi_slp_type == 2);
 }
 
 static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp)
@@ -567,9 +568,11 @@ void *acpi_find_wakeup_vector(void)
 	return wake_vec;
 }
 
+#if CONFIG_SMP
 extern char *lowmem_backup;
 extern char *lowmem_backup_ptr;
 extern int lowmem_backup_size;
+#endif
 
 #define WAKEUP_BASE 0x600
 
@@ -588,12 +591,14 @@ void acpi_jump_to_wakeup(void *vector)
 		return;
 	}
 
+#if CONFIG_SMP
 	// FIXME: This should go into the ACPI backup memory, too. No pork saussages.
 	/*
 	 * Just restore the SMP trampoline and continue with wakeup on
 	 * assembly level.
 	 */
 	memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
+#endif
 
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index eecefcd5bf..202f521fdb 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -191,8 +191,10 @@ extern u8 acpi_slp_type;
 void cbmem_initialize(void)
 {
 #if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type == 3) {
+	printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type);
+	if (acpi_slp_type == 3 || acpi_slp_type == 2) {
 		if (!cbmem_reinit(high_tables_base)) {
+			printk(BIOS_DEBUG, "cbmem_reinit failed\n");
 			/* Something went wrong, our high memory area got wiped */
 			acpi_slp_type = 0;
 			cbmem_init(high_tables_base, high_tables_size);
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 5e6411ce1b..c5befa00b3 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -21,27 +21,51 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
 {
-	/* For now only define 2 power states:
-	 *  - S0 which is fully on
-	 *  - S5 which is soft off
-	 * Any others would involve declaring the wake up methods.
-	 */
-
-	/* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
 	/*
-	000b / 0x0: soft off/suspend to disk (soff/std)			s5
-	001b / 0x1: suspend to ram (str)				s3
-	010b / 0x2: powered on suspend, context lost (poscl)		s1
-	011b / 0x3: powered on suspend, cpu context lost (posccl)	s2
-	100b / 0x4: powered on suspend, context maintained (pos)	s4
-	101b / 0x5: working (clock control)				s0
-	110b / 0x6: reserved
-	111b / 0x7: reserved
-	*/
+	 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+	 *
+	 * 0: soft off/suspend to disk					S5
+	 * 1: suspend to ram						S3
+	 * 2: powered on suspend, context lost				S2
+	 *    Note: 'context lost' means the CPU restarts at the reset
+	 *          vector
+	 * 3: powered on suspend, CPU context lost			S1
+	 *    Note: Looks like 'CPU context lost' does _not_ mean the
+	 *          CPU restarts at the reset vector. Most likely only
+	 *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+	 * 4: powered on suspend, context maintained			S1
+	 * 5: working (clock control)					S0
+	 * 6: reserved
+	 * 7: reserved
+	 */
 	Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
 	Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })
 	Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
 
+	OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)
+	Field (SIO1, ByteAcc, NoLock, Preserve)
+	{
+		FANP,	1, /* CPU/case fan power */
+		Offset (0x01),
+		PLED,	1,
+	}
+
+	Method (\_PTS, 1, NotSerialized)
+	{
+		/* Disable fan, blink power led */
+		Store (Zero, FANP)
+		Store (Zero, PLED)
+	}
+
+	Method (\_WAK, 1, NotSerialized)
+	{
+		/* Re-enable fan, stop power led blinking */
+		Store (One, FANP)
+		Store (One, PLED)
+		/* wake OK */
+		Return(Package(0x02){0x00, 0x00})
+	}
+
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
 	{
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index 9b037feb0e..3b5679657f 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -1,6 +1,7 @@
 config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select TINY_BOOTBLOCK
+	select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 940a17d2b5..9e2c3ebed9 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -26,6 +26,7 @@ driver-y +=  smbus.c
 driver-y +=  reset.c
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c
+driver-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
 
 romstage-y += early_pm.c
 romstage-y += early_smbus.c
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index b1a51c6a8a..65af02abb0 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -31,6 +31,11 @@
 #include "i82371eb.h"
 #include "smbus.h"
 
+#if CONFIG_HAVE_ACPI_RESUME == 1
+extern u8 acpi_slp_type;
+int acpi_get_sleep_type(void);
+#endif
+
 static void pwrmgt_enable(struct device *dev)
 {
 	struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
@@ -87,7 +92,13 @@ static void pwrmgt_enable(struct device *dev)
 	outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
 	outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
 
-	/* set pmcntrl default */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+	/* this reads PMCNTRL, so we have to call it before writing the
+	 * default value */
+	acpi_slp_type = acpi_get_sleep_type();
+#endif
+
+	/* set PMCNTRL default */
 	outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
 }
 
diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c
new file mode 100644
index 0000000000..f018ad9adf
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/wakeup.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include "i82371eb.h"
+
+int acpi_get_sleep_type(void);
+
+/*
+ * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+ *
+ * 0: soft off/suspend to disk					S5
+ * 1: suspend to ram						S3
+ * 2: powered on suspend, context lost				S2
+ *    Note: 'context lost' means the CPU restarts at the reset
+ *          vector
+ * 3: powered on suspend, CPU context lost			S1
+ *    Note: Looks like 'CPU context lost' does _not_ mean the
+ *          CPU restarts at the reset vector. Most likely only
+ *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * 4: powered on suspend, context maintained			S1
+ * 5: working (clock control)					S0
+ * 6: reserved
+ * 7: reserved
+ */
+static const u8 acpi_sus_to_slp_typ[8] = {
+	5, 3, 2, 1, 1, 0, 0, 0
+};
+
+int acpi_get_sleep_type(void)
+{
+	u16 reg, result;
+
+	reg = inw(DEFAULT_PMBASE + PMCNTRL);
+	result = acpi_sus_to_slp_typ[(reg >> 10) & 7];
+
+	printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg);
+
+	return result;
+}