diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/amd/onyx_poc/devicetree.cb | 214 | ||||
| -rw-r--r-- | src/soc/amd/genoa_poc/chipset.cb | 320 | ||||
| -rw-r--r-- | src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c | 2 |
3 files changed, 336 insertions, 200 deletions
diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index 578bc42f7a..c1b2f5c28c 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,36 +55,30 @@ chip soc/amd/genoa_poc device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - device ref gpp_bridge_0_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P2 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "48" - register "end_lane" = "63" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end # dummy for configuring mpio - end - end - device ref gpp_bridge_0_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G2 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "112" - register "end_lane" = "127" - register "gpio_group" = "1" - register "aspm" = "L1" - register "hotplug" = "ServerExpress" - device generic 0 on end - end - end - device ref gpp_bridge_0_0_c on - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "IFTYPE_PCIE" - register "start_lane" = "128" - register "end_lane" = "131" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "48" + register "end_lane" = "63" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_0_0_a on end + end + chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "112" + register "end_lane" = "127" + register "gpio_group" = "1" + register "aspm" = "L1" + register "hotplug" = "ServerExpress" + device ref gpp_bridge_0_0_b on end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "128" + register "end_lane" = "131" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_0_0_c on end end device ref gpp_bridge_0_a on device ref xhci_0 on end @@ -99,51 +93,43 @@ chip soc/amd/genoa_poc device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - device ref gpp_bridge_1_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P3 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "16" - register "end_lane" = "31" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end - end - device ref gpp_bridge_1_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G3 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "80" - register "end_lane" = "95" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "16" + register "end_lane" = "31" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_1_0_a on end + end + chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "80" + register "end_lane" = "95" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_1_0_b on end end end device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - device ref gpp_bridge_2_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P1 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "32" - register "end_lane" = "47" - register "gpio_group" = "1" - register "aspm" = "L1" - register "hotplug" = "ServerExpress" - device generic 0 on end - end - end - device ref gpp_bridge_2_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G1 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "64" - register "end_lane" = "79" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "32" + register "end_lane" = "47" + register "gpio_group" = "1" + register "aspm" = "L1" + register "hotplug" = "ServerExpress" + device ref gpp_bridge_2_0_a on end + end + chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "64" + register "end_lane" = "79" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_2_0_b on end end end @@ -151,56 +137,46 @@ chip soc/amd/genoa_poc device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - device ref gpp_bridge_3_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P0 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "0" - register "end_lane" = "15" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end - end - device ref gpp_bridge_3_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G0 - register "type" = "IFTYPE_PCIE" - register "start_lane" = "96" - register "end_lane" = "111" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end - end - device ref gpp_bridge_3_0_c on # WAFL - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "IFTYPE_PCIE" - register "start_lane" = "132" - register "end_lane" = "133" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end - end - device ref gpp_bridge_3_1_c on # BMC - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "IFTYPE_PCIE" - register "start_lane" = "134" - register "end_lane" = "134" - register "gpio_group" = "1" - register "aspm" = "L1" - register "bmc" = "1" - device generic 0 on end - end - end - device ref gpp_bridge_3_2_c on # BMC - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "IFTYPE_PCIE" - register "start_lane" = "135" - register "end_lane" = "135" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "0" + register "end_lane" = "15" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_0_a on end + end + chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + register "type" = "IFTYPE_PCIE" + register "start_lane" = "96" + register "end_lane" = "111" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_0_b on end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "132" + register "end_lane" = "133" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_0_c on end # WAFL + end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "134" + register "end_lane" = "134" + register "gpio_group" = "1" + register "aspm" = "L1" + register "bmc" = "1" + device ref gpp_bridge_3_1_c on end # BMC + end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "135" + register "end_lane" = "135" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_2_c on end # BMC end device ref gpp_bridge_3_a on device ref xhci_3 on end diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index dccffde822..92dcb5df96 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -16,36 +16,80 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_0 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_0_0_a off end - device pci 01.2 alias gpp_bridge_0_1_a off end - device pci 01.3 alias gpp_bridge_0_2_a off end - device pci 01.4 alias gpp_bridge_0_3_a off end - device pci 01.5 alias gpp_bridge_0_4_a off end - device pci 01.6 alias gpp_bridge_0_5_a off end - device pci 01.7 alias gpp_bridge_0_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_0_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_0_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_0_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_0_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_0_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_0_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_0_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0_7_a off end - device pci 02.2 alias gpp_bridge_0_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_0_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_0_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_0_0_b off end - device pci 03.2 alias gpp_bridge_0_1_b off end - device pci 03.3 alias gpp_bridge_0_2_b off end - device pci 03.4 alias gpp_bridge_0_3_b off end - device pci 03.5 alias gpp_bridge_0_4_b off end - device pci 03.6 alias gpp_bridge_0_5_b off end - device pci 03.7 alias gpp_bridge_0_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_0_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_0_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_0_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_0_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_0_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_0_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_0_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_0_7_b off end - device pci 04.2 alias gpp_bridge_0_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_0_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_0_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable - device pci 05.1 alias gpp_bridge_0_0_c off end - device pci 05.2 alias gpp_bridge_0_1_c off end - device pci 05.3 alias gpp_bridge_0_2_c off end - device pci 05.4 alias gpp_bridge_0_3_c off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.1 alias gpp_bridge_0_0_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.2 alias gpp_bridge_0_1_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.3 alias gpp_bridge_0_2_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.4 alias gpp_bridge_0_3_c off end + end device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0 @@ -84,30 +128,66 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_1 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_1_0_a off end - device pci 01.2 alias gpp_bridge_1_1_a off end - device pci 01.3 alias gpp_bridge_1_2_a off end - device pci 01.4 alias gpp_bridge_1_3_a off end - device pci 01.5 alias gpp_bridge_1_4_a off end - device pci 01.6 alias gpp_bridge_1_5_a off end - device pci 01.7 alias gpp_bridge_1_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_1_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_1_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_1_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_1_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_1_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_1_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_1_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_1_7_a off end - device pci 02.2 alias gpp_bridge_1_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_1_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_1_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_1_0_b off end - device pci 03.2 alias gpp_bridge_1_1_b off end - device pci 03.3 alias gpp_bridge_1_2_b off end - device pci 03.4 alias gpp_bridge_1_3_b off end - device pci 03.5 alias gpp_bridge_1_4_b off end - device pci 03.6 alias gpp_bridge_1_5_b off end - device pci 03.7 alias gpp_bridge_1_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_1_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_1_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_1_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_1_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_1_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_1_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_1_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_1_7_b off end - device pci 04.2 alias gpp_bridge_1_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_1_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_1_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable @@ -127,30 +207,66 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_2 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_2_0_a off end - device pci 01.2 alias gpp_bridge_2_1_a off end - device pci 01.3 alias gpp_bridge_2_2_a off end - device pci 01.4 alias gpp_bridge_2_3_a off end - device pci 01.5 alias gpp_bridge_2_4_a off end - device pci 01.6 alias gpp_bridge_2_5_a off end - device pci 01.7 alias gpp_bridge_2_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_2_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_2_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_2_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_2_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_2_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_2_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_2_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_2_7_a off end - device pci 02.2 alias gpp_bridge_2_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_2_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_2_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_2_0_b off end - device pci 03.2 alias gpp_bridge_2_1_b off end - device pci 03.3 alias gpp_bridge_2_2_b off end - device pci 03.4 alias gpp_bridge_2_3_b off end - device pci 03.5 alias gpp_bridge_2_4_b off end - device pci 03.6 alias gpp_bridge_2_5_b off end - device pci 03.7 alias gpp_bridge_2_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_2_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_2_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_2_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_2_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_2_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_2_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_2_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_2_7_b off end - device pci 04.2 alias gpp_bridge_2_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_2_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_2_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable @@ -170,36 +286,80 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_3 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_3_0_a off end - device pci 01.2 alias gpp_bridge_3_1_a off end - device pci 01.3 alias gpp_bridge_3_2_a off end - device pci 01.4 alias gpp_bridge_3_3_a off end - device pci 01.5 alias gpp_bridge_3_4_a off end - device pci 01.6 alias gpp_bridge_3_5_a off end - device pci 01.7 alias gpp_bridge_3_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_3_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_3_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_3_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_3_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_3_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_3_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_3_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_3_7_a off end - device pci 02.2 alias gpp_bridge_3_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_3_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_3_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_3_0_b off end - device pci 03.2 alias gpp_bridge_3_1_b off end - device pci 03.3 alias gpp_bridge_3_2_b off end - device pci 03.4 alias gpp_bridge_3_3_b off end - device pci 03.5 alias gpp_bridge_3_4_b off end - device pci 03.6 alias gpp_bridge_3_5_b off end - device pci 03.7 alias gpp_bridge_3_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_3_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_3_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_3_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_3_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_3_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_3_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_3_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_3_7_b off end - device pci 04.2 alias gpp_bridge_3_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_3_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_3_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable - device pci 05.1 alias gpp_bridge_3_0_c off end - device pci 05.2 alias gpp_bridge_3_1_c off end - device pci 05.3 alias gpp_bridge_3_2_c off end - device pci 05.4 alias gpp_bridge_3_3_c off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.1 alias gpp_bridge_3_0_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.2 alias gpp_bridge_3_1_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.3 alias gpp_bridge_3_2_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.4 alias gpp_bridge_3_3_c off end + end device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_3_a off diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 2d32ca5e64..6d811ce47d 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -198,5 +198,5 @@ void configure_mpio(void) for (struct device *dev = &dev_root; dev; dev = dev->next) if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops && dev->chip_info != dev->upstream->dev->chip_info) - per_device_config(mpio_data, dev->upstream->dev, dev->chip_info); + per_device_config(mpio_data, dev, dev->chip_info); } |