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-rw-r--r--src/soc/intel/alderlake/chip.h3
-rw-r--r--src/soc/intel/alderlake/fsp_params.c7
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 3192478f77..270400b341 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -492,6 +492,9 @@ struct soc_intel_alderlake_config {
POWER_CYCLE_DURATION_3S,
POWER_CYCLE_DURATION_4S,
} pch_reset_power_cycle_duration;
+
+ /* Platform Power Pmax */
+ uint16_t PsysPmax;
};
typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 8003471128..4ae25371cb 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -652,6 +652,13 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
s_cfg->PchPmSlpS3MinAssert,
s_cfg->PchPmSlpAMinAssert,
power_cycle_duration);
+
+ /* Set PsysPmax if it is available from DT */
+ if (config->PsysPmax) {
+ printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
+ /* PsysPmax is in unit of 1/8 Watt */
+ s_cfg->PsysPmax = config->PsysPmax * 8;
+ }
}
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,