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-rw-r--r--src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index d31cafc83a..9a71e959c3 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -11,6 +11,25 @@ chip soc/intel/meteorlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
+ register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
+ register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
+
+ register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
+ register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
+
+ register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
+ register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
+ register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
+ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
+
# S0ix enable
register "s0ix_enable" = "1"