diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/mt8188/Kconfig | 18 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/Makefile.inc | 22 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/bootblock.c | 9 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/emi.c | 13 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/addressmap.h | 74 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/emi.h | 15 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/memlayout.ld | 72 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/pll.h | 23 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/spi.h | 13 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/timer.h | 13 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/soc.c | 30 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/spi.c | 22 |
12 files changed, 324 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8188/Kconfig b/src/soc/mediatek/mt8188/Kconfig new file mode 100644 index 0000000000..0bbc4afeab --- /dev/null +++ b/src/soc/mediatek/mt8188/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8188 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8188 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc new file mode 100644 index 0000000000..9a2ff7dc5a --- /dev/null +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -0,0 +1,22 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8188),y) + +all-$(CONFIG_SPI_FLASH) += spi.c +all-y += ../common/timer.c +all-y += ../common/uart.c + +bootblock-y += bootblock.c +bootblock-y += ../common/mmu_operations.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c + +ramstage-y += emi.c +ramstage-y += soc.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8188/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8188/bootblock.c b/src/soc/mediatek/mt8188/bootblock.c new file mode 100644 index 0000000000..f48e78c309 --- /dev/null +++ b/src/soc/mediatek/mt8188/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu_operations.h> + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); +} diff --git a/src/soc/mediatek/mt8188/emi.c b/src/soc/mediatek/mt8188/emi.c new file mode 100644 index 0000000000..bb503bb6ca --- /dev/null +++ b/src/soc/mediatek/mt8188/emi.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 3.7 + */ + +#include <soc/emi.h> + +size_t sdram_size(void) +{ + return (size_t)4 * GiB; +} diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h new file mode 100644 index 0000000000..d198dd7f47 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_ADDRESSMAP_H__ + +/* + * This file is created based on MT8188 Application Processor Registers + */ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS + 0x00000000, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + SYSTIMER_BASE = IO_PHYS + 0x00017000, + PMIF_SPI_BASE = IO_PHYS + 0x00024000, + PMICSPI_MST_BASE = IO_PHYS + 0x00025000, + PMIF_SPMI_BASE = IO_PHYS + 0x00027000, + SPMI_MST_BASE = IO_PHYS + 0x00029000, + EMI0_BASE = IO_PHYS + 0x00219000, + EMI1_BASE = IO_PHYS + 0x0021D000, + I2C0_DMA_BASE = IO_PHYS + 0x00220080, + I2C1_DMA_BASE = IO_PHYS + 0x00220100, + I2C2_DMA_BASE = IO_PHYS + 0x00220180, + I2C3_DMA_BASE = IO_PHYS + 0x00220280, + I2C4_DMA_BASE = IO_PHYS + 0x00220380, + I2C5_DMA_BASE = IO_PHYS + 0x00220480, + I2C6_DMA_BASE = IO_PHYS + 0x00220600, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, + DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, + DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, + DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, + UART0_BASE = IO_PHYS + 0x01001100, + UART1_BASE = IO_PHYS + 0x01001200, + UART2_BASE = IO_PHYS + 0x01001300, + UART3_BASE = IO_PHYS + 0x01001400, + AUXADC_BASE = IO_PHYS + 0x01002000, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01018000, + SPI5_BASE = IO_PHYS + 0x01019000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, + MSDC0_BASE = IO_PHYS + 0x01230000, + MSDC1_BASE = IO_PHYS + 0x01240000, + I2C0_BASE = IO_PHYS + 0x01280000, + I2C2_BASE = IO_PHYS + 0x01281000, + I2C3_BASE = IO_PHYS + 0x01282000, + SFLASH_REG_BASE = IO_PHYS + 0x0132C000, + IOCFG_RM_BASE = IO_PHYS + 0x01C00000, + I2C1_BASE = IO_PHYS + 0x01E00000, + I2C4_BASE = IO_PHYS + 0x01E01000, + IOCFG_LT_BASE = IO_PHYS + 0x01E10000, + IOCFG_LM_BASE = IO_PHYS + 0x01E20000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E40000, + IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, + MSDC1_TOP_BASE = IO_PHYS + 0x01EB0000, + I2C5_BASE = IO_PHYS + 0x01EC0000, + I2C6_BASE = IO_PHYS + 0x01EC1000, + MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, +}; +#endif diff --git a/src/soc/mediatek/mt8188/include/soc/emi.h b/src/soc/mediatek/mt8188/include/soc/emi.h new file mode 100644 index 0000000000..eeefdd3cab --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/emi.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef SOC_MEDIATEK_MT8188_EMI_H +#define SOC_MEDIATEK_MT8188_EMI_H + +#include <stddef.h> + +size_t sdram_size(void); + +#endif /* SOC_MEDIATEK_MT8188_EMI_H */ diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld new file mode 100644 index 0000000000..d8db9df55a --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <memlayout.h> +#include <arch/header.ld> +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 64K) +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +SECTIONS +{ + /* MT8188 has 192KB SRAM in total. */ + SRAM_START(0x00100000) + /* Regions that need to stay in SRAM. */ + TTB(0x00100000, 28K) + DMA_COHERENT(0x00107000, 4K) + STACK(0x00108000, 15K) + WATCHDOG_TOMBSTONE(0x0010bc00, 4) + /* EMPTY(0x0010bc04, 29K - 4) */ + /* + * MCUPM exchanges data with kernel driver using SRAM 0x00113000 ~ + * 0x0011ffff. The address is hardcoded in MCUPM image. + */ + REGION(mcufw_reserved, 0x00113000, 52K, 4K) + /* End of regions that need to stay in SRAM. */ + /* Regions can be moved to SRAM_L2C. */ + CBFS_MCACHE(0x00120000, 16k) + VBOOT2_WORK(0x00124000, 12K) + FMAP_CACHE(0x00127000, 2k) + TPM_TCPA_LOG(0x00127800, 2k) + TIMESTAMP(0x00128000, 1k) + /* End of regions that can also be moved to SRAM_L2C. */ + /* EMPTY(0x00128400, 31K) */ + SRAM_END(0x00130000) + + /* + * The L3 is 2MB in total. The bootROM has configured half of the L3 cache as SRAM + *(SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you + * can't reconfigure whole L3 as SRAM). + */ + SRAM_L2C_START(0x00200000) + /* + * The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address + * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started. + * To move the address, gen-bl-img.py also needs to be modified accordingly. + */ + BOOTBLOCK(0x00201000, 60K) + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + * To move the address, dram.elf also needs to be modified accordingly. + */ + DRAM_INIT_CODE(0x00210000, 300K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0025b000, 272K) + PRERAM_CBFS_CACHE(0x0029f000, 48K) + PRERAM_CBMEM_CONSOLE(0x002ab000, 340K) + SRAM_L2C_END(0x00300000) + + DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 256K) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/mediatek/mt8188/include/soc/pll.h b/src/soc/mediatek/mt8188/include/soc/pll.h new file mode 100644 index 0000000000..6b6c123d3e --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/pll.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 4.1 + */ + +#ifndef SOC_MEDIATEK_MT8188_PLL_H +#define SOC_MEDIATEK_MT8188_PLL_H + +#include <soc/pll_common.h> + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, +}; + +/* top_mux rate */ +enum { + UART_HZ = CLK26M_HZ, +}; + +#endif /* SOC_MEDIATEK_MT8188_PLL_H */ diff --git a/src/soc/mediatek/mt8188/include/soc/spi.h b/src/soc/mediatek/mt8188/include/soc/spi.h new file mode 100644 index 0000000000..e851b0218a --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 5.8 + */ + +#ifndef MTK_MT8188_SPI_H +#define MTK_MT8188_SPI_H + +#include <spi-generic.h> + +#endif diff --git a/src/soc/mediatek/mt8188/include/soc/timer.h b/src/soc/mediatek/mt8188/include/soc/timer.h new file mode 100644 index 0000000000..54b4e84435 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/timer.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8188_TIMER_H +#define SOC_MEDIATEK_MT8188_TIMER_H + +#include <soc/timer_v2.h> + +#endif diff --git a/src/soc/mediatek/mt8188/soc.c b/src/soc/mediatek/mt8188/soc.c new file mode 100644 index 0000000000..cce21a0b0c --- /dev/null +++ b/src/soc/mediatek/mt8188/soc.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = noop_set_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8188_ops = { + CHIP_NAME("SOC Mediatek MT8188") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8188/spi.c b/src/soc/mediatek/mt8188/spi.c new file mode 100644 index 0000000000..30eff1b7f3 --- /dev/null +++ b/src/soc/mediatek/mt8188/spi.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 5.8 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/spi.h> + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_flash_ctrlr, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |