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-rw-r--r--src/soc/amd/cezanne/include/soc/data_fabric.h9
-rw-r--r--src/soc/amd/common/block/data_fabric/data_fabric_helper.c10
-rw-r--r--src/soc/amd/common/block/data_fabric/domain.c4
-rw-r--r--src/soc/amd/common/block/include/amdblocks/data_fabric.h6
-rw-r--r--src/soc/amd/glinda/include/soc/data_fabric.h9
-rw-r--r--src/soc/amd/mendocino/include/soc/data_fabric.h9
-rw-r--r--src/soc/amd/phoenix/include/soc/data_fabric.h9
-rw-r--r--src/soc/amd/picasso/include/soc/data_fabric.h9
8 files changed, 30 insertions, 35 deletions
diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h
index 100529e5fb..eac8801113 100644
--- a/src/soc/amd/cezanne/include/soc/data_fabric.h
+++ b/src/soc/amd/cezanne/include/soc/data_fabric.h
@@ -6,11 +6,10 @@
#include <amdblocks/data_fabric_defs.h>
#include <types.h>
-/* D18F0 - Fabric Configuration registers */
-#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200)
-#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
-#define D18F0_MMIO_SHIFT 16
-#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208)
+#define DF_MMIO_BASE0 DF_REG_ID(0, 0x200)
+#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
+#define DF_MMIO_SHIFT 16
+#define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208)
#define DF_MMIO_REG_SET_SIZE 4
#define DF_MMIO_REG_SET_COUNT 8
diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
index 812e0d442c..e19b278cc0 100644
--- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
+++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
@@ -57,11 +57,11 @@ void data_fabric_print_mmio_conf(void)
/* Base and limit address registers don't contain the lower address bits, but
are shifted by D18F0_MMIO_SHIFT bits */
base = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_BASE(i))
- << D18F0_MMIO_SHIFT;
+ << DF_MMIO_SHIFT;
limit = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_LIMIT(i))
- << D18F0_MMIO_SHIFT;
+ << DF_MMIO_SHIFT;
/* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */
- limit += (1 << D18F0_MMIO_SHIFT) - 1;
+ limit += (1 << DF_MMIO_SHIFT) - 1;
printk(BIOS_SPEW, " %2u %16llx %16llx %8x %s %s %s %4x\n",
i, base, limit, control.raw,
control.re ? "x" : " ",
@@ -121,8 +121,8 @@ void data_fabric_set_mmio_np(void)
int reg;
uint32_t base, limit;
union df_mmio_control ctrl;
- const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
- const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
+ const uint32_t np_bot = HPET_BASE_ADDRESS >> DF_MMIO_SHIFT;
+ const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> DF_MMIO_SHIFT;
data_fabric_print_mmio_conf();
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index f28bb1228f..9f0f48c325 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -41,8 +41,8 @@ static void data_fabric_get_mmio_base_size(unsigned int reg,
const uint32_t base_reg = data_fabric_broadcast_read32(DF_MMIO_BASE(reg));
const uint32_t limit_reg = data_fabric_broadcast_read32(DF_MMIO_LIMIT(reg));
/* The raw register values are bits 47..16 of the actual address */
- *mmio_base = (resource_t)base_reg << D18F0_MMIO_SHIFT;
- *mmio_limit = (((resource_t)limit_reg + 1) << D18F0_MMIO_SHIFT) - 1;
+ *mmio_base = (resource_t)base_reg << DF_MMIO_SHIFT;
+ *mmio_limit = (((resource_t)limit_reg + 1) << DF_MMIO_SHIFT) - 1;
}
static void print_df_mmio_outside_of_cpu_mmio_error(unsigned int reg)
diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h
index ad1f97bafb..911b504cb6 100644
--- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h
+++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h
@@ -18,9 +18,9 @@
#define DF_MMIO_REG_OFFSET(instance) ((instance) * DF_MMIO_REG_SET_SIZE * sizeof(uint32_t))
/* The number of data fabric MMIO registers is SoC-specific */
-#define DF_MMIO_BASE(reg) (D18F0_MMIO_BASE0 + DF_MMIO_REG_OFFSET(reg))
-#define DF_MMIO_LIMIT(reg) (D18F0_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg))
-#define DF_MMIO_CONTROL(reg) (D18F0_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg))
+#define DF_MMIO_BASE(reg) (DF_MMIO_BASE0 + DF_MMIO_REG_OFFSET(reg))
+#define DF_MMIO_LIMIT(reg) (DF_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg))
+#define DF_MMIO_CONTROL(reg) (DF_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg))
/* Last 12GB of the usable address space are reserved */
#define DF_RESERVED_TOP_12GB_MMIO_SIZE (12ULL * GiB)
diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h
index 3ddac62559..d34c4daeb1 100644
--- a/src/soc/amd/glinda/include/soc/data_fabric.h
+++ b/src/soc/amd/glinda/include/soc/data_fabric.h
@@ -6,11 +6,10 @@
#include <amdblocks/data_fabric_defs.h>
#include <types.h>
-/* D18F0 - Fabric Configuration registers */
-#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0xD80)
-#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0xD84)
-#define D18F0_MMIO_SHIFT 16
-#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0xD88)
+#define DF_MMIO_BASE0 DF_REG_ID(0, 0xD80)
+#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xD84)
+#define DF_MMIO_SHIFT 16
+#define DF_MMIO_CTRL0 DF_REG_ID(0, 0xD88)
#define DF_MMIO_REG_SET_SIZE 4
#define DF_MMIO_REG_SET_COUNT 8
diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h
index ebcaf2b0b4..c20f252b20 100644
--- a/src/soc/amd/mendocino/include/soc/data_fabric.h
+++ b/src/soc/amd/mendocino/include/soc/data_fabric.h
@@ -6,11 +6,10 @@
#include <amdblocks/data_fabric_defs.h>
#include <types.h>
-/* D18F0 - Fabric Configuration registers */
-#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200)
-#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
-#define D18F0_MMIO_SHIFT 16
-#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208)
+#define DF_MMIO_BASE0 DF_REG_ID(0, 0x200)
+#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
+#define DF_MMIO_SHIFT 16
+#define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208)
#if CONFIG(SOC_AMD_REMBRANDT)
#define DF_MMIO_REG_SET_SIZE 3
diff --git a/src/soc/amd/phoenix/include/soc/data_fabric.h b/src/soc/amd/phoenix/include/soc/data_fabric.h
index 790b868ef8..ccb830fee0 100644
--- a/src/soc/amd/phoenix/include/soc/data_fabric.h
+++ b/src/soc/amd/phoenix/include/soc/data_fabric.h
@@ -6,11 +6,10 @@
#include <amdblocks/data_fabric_defs.h>
#include <types.h>
-/* D18F0 - Fabric Configuration registers */
-#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0xD80)
-#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0xD84)
-#define D18F0_MMIO_SHIFT 16
-#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0xD88)
+#define DF_MMIO_BASE0 DF_REG_ID(0, 0xD80)
+#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xD84)
+#define DF_MMIO_SHIFT 16
+#define DF_MMIO_CTRL0 DF_REG_ID(0, 0xD88)
#define DF_MMIO_REG_SET_SIZE 4
#define DF_MMIO_REG_SET_COUNT 8
diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h
index 382de8a73e..fa5c0df607 100644
--- a/src/soc/amd/picasso/include/soc/data_fabric.h
+++ b/src/soc/amd/picasso/include/soc/data_fabric.h
@@ -6,11 +6,10 @@
#include <amdblocks/data_fabric_defs.h>
#include <types.h>
-/* D18F0 - Fabric Configuration registers */
-#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200)
-#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
-#define D18F0_MMIO_SHIFT 16
-#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208)
+#define DF_MMIO_BASE0 DF_REG_ID(0, 0x200)
+#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
+#define DF_MMIO_SHIFT 16
+#define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208)
#define DF_MMIO_REG_SET_SIZE 4
#define DF_MMIO_REG_SET_COUNT 8
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:42:25 +0000