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Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 33be8623f7..3155d04f82 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # S0ix enable + register "s0ix_enable" = "1" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 |