diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/chip.h | 37 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 15 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 178dd7cda1..2c3ec030c8 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -94,6 +94,20 @@ enum lpm_state_mask { | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, }; +/* + * As per definition from FSP header: + * - [0] for IA + * - [1] for GT + * - [2] for SA + * - [3] through [5] are reserved + */ +enum vr_domain { + VR_DOMAIN_IA, + VR_DOMAIN_GT, + VR_DOMAIN_SA, + NUM_VR_DOMAINS +}; + struct soc_intel_meteorlake_config { /* Common struct containing soc config data required by common code */ @@ -245,6 +259,29 @@ struct soc_intel_meteorlake_config { /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; + /* + * When enabled, this feature makes the SoC throttle when the power + * consumption exceeds the I_TRIP threshold. + * + * FSPs sets a by default I_TRIP threshold adapted to the current SoC + * and assuming a Voltage Regulator error accuracy of 6.5%. + */ + bool enable_fast_vmode[NUM_VR_DOMAINS]; + + /* + * Current Excursion Protection needs to be set for each VR domain + * in order to be able to enable fast Vmode. + */ + bool cep_enable[NUM_VR_DOMAINS]; + + /* + * VR Fast Vmode I_TRIP threshold. + * 0-255A in 1/4 A units. Example: 400 = 100A + * This setting overrides the default value set by FSPs when Fast VMode + * is enabled. + */ + uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS]; + uint8_t PmTimerDisabled; /* * SerialIO device mode selection: diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index fd634ecae0..bb5b6e7d97 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -224,6 +224,20 @@ static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, m_cfg->SmbusEnable = is_devfn_enabled(PCI_DEVFN_SMBUS); } +static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_meteorlake_config *config) +{ + /* FastVmode Settings for VR domains */ + for (size_t domain = 0; domain < NUM_VR_DOMAINS; domain++) { + m_cfg->CepEnable[domain] = config->cep_enable[domain]; + if (m_cfg->CepEnable[domain]) { + m_cfg->EnableFastVmode[domain] = config->enable_fast_vmode[domain]; + if (m_cfg->EnableFastVmode[domain]) + m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain]; + } + } +} + static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { @@ -360,6 +374,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, fill_fspm_usb4_params, fill_fspm_vtd_params, fill_fspm_trace_params, + fill_fspm_vr_config_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |