diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 55 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/iommu.c | 48 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 2 |
5 files changed, 47 insertions, 63 deletions
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ba55466026..c77f3bac6a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -43,7 +43,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += iommu.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index fd3d34f2de..0c6ef7ebdf 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 secunet Security Networks AG * Copyright (C) 2011 Google Inc + * Copyright (C) 2018 Patrick Rudolph <patrick.rudolph@9elements.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +19,8 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/mmio.h> +#include <device/device.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> @@ -25,6 +29,41 @@ #include "sandybridge.h" +static void systemagent_vtd_init(void) +{ + const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + if (capid0_a & (1 << 23)) + return; + + /* setup BARs */ + MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; + MCHBAR32(0x5400) = IOMMU_BASE1 | 1; + MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; + MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + + /* lock policies */ + write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + + const struct device *const azalia = pcidev_on_root(0x1b, 0); + if (azalia && azalia->enabled) { + write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); + write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + } else { + write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + } +} + +static void enable_pam_region(void) +{ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); +} + static void sandybridge_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); @@ -36,15 +75,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); - /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - printk(BIOS_DEBUG, " done\n"); } @@ -156,7 +186,7 @@ static void start_peg_link_training(void) } } -void sandybridge_early_initialization(void) +void systemagent_early_init(void) { u32 capid0_a; u32 deven; @@ -179,8 +209,11 @@ void sandybridge_early_initialization(void) /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(); + /* Set C0000-FFFFF to access RAM on both reads and writes */ + enable_pam_region(); + /* Setup IOMMU BARs */ - sandybridge_init_iommu(); + systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c deleted file mode 100644 index 339397d068..0000000000 --- a/src/northbridge/intel/sandybridge/iommu.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <device/device.h> -#include <device/pci_def.h> - -#include "sandybridge.h" - -void sandybridge_init_iommu(void) -{ - const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); - if (capid0_a & (1 << 23)) - return; - - /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; - - /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); - - const struct device *const azalia = pcidev_on_root(0x1b, 0); - if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); - } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); - } -} diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 76b3088388..2cef5f2605 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -74,8 +74,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Perform some early chipset initialization required * before RAM initialization can work */ - sandybridge_early_initialization(); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + systemagent_early_init(); + printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); s3resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 77165f6931..88b7b56864 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -216,7 +216,7 @@ static inline void barrier(void) { asm("" ::: "memory"); } void intel_sandybridge_finalize_smm(void); #else /* !__SMM__ */ int bridge_silicon_revision(void); -void sandybridge_early_initialization(void); +void systemagent_early_init(void); void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); |