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-rw-r--r--src/soc/intel/elkhartlake/chip.h1
-rw-r--r--src/soc/intel/elkhartlake/fsp_params.c15
2 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 8743eb0871..b15d78a1ee 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -338,6 +338,7 @@ struct soc_intel_elkhartlake_config {
*/
uint8_t DdiPortAConfig;
uint8_t DdiPortBConfig;
+ uint8_t DdiPortCConfig;
/* Enable(1)/Disable(0) HPD */
uint8_t DdiPortAHpd;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 8d802f42be..11fc2d3f75 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -259,10 +259,23 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
/* Display config */
+ params->DdiPortAConfig = config->DdiPortAConfig;
+ params->DdiPortBConfig = config->DdiPortBConfig;
+ params->DdiPortCConfig = config->DdiPortCConfig;
params->DdiPortAHpd = config->DdiPortAHpd;
- params->DdiPortADdc = config->DdiPortADdc;
+ params->DdiPortBHpd = config->DdiPortBHpd;
params->DdiPortCHpd = config->DdiPortCHpd;
+ params->DdiPort1Hpd = config->DdiPort1Hpd;
+ params->DdiPort2Hpd = config->DdiPort2Hpd;
+ params->DdiPort3Hpd = config->DdiPort3Hpd;
+ params->DdiPort4Hpd = config->DdiPort4Hpd;
+ params->DdiPortADdc = config->DdiPortADdc;
+ params->DdiPortBDdc = config->DdiPortBDdc;
params->DdiPortCDdc = config->DdiPortCDdc;
+ params->DdiPort1Ddc = config->DdiPort1Ddc;
+ params->DdiPort2Ddc = config->DdiPort2Ddc;
+ params->DdiPort3Ddc = config->DdiPort3Ddc;
+ params->DdiPort4Ddc = config->DdiPort4Ddc;
/* Intel Speed Step */
params->Eist = config->eist_enable;