diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/cezanne/psp_verstage/chipset.c | 10 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/psp_verstage/svc.c | 7 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h | 1 |
3 files changed, 8 insertions, 10 deletions
diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 30f613a492..41d318e0eb 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -40,13 +40,3 @@ void platform_report_mode(int developer_mode_enabled) else svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION); } - - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) -{ - return 0; -} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 78f71260a4..12fccc38f7 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -140,3 +140,10 @@ uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); return retval; } + +uint32_t svc_write_postcode(uint32_t postcode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval); + return retval; +} diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index ff2144d159..4cf9e70686 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -51,6 +51,7 @@ #define SVC_SHA 0x69 #define SVC_CCP_DMA 0x6A #define SVC_SET_PLATFORM_BOOT_MODE 0x6C +#define SVC_WRITE_POSTCODE 0x6D struct mod_exp_params { char *pExponent; // Exponent address |