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-rw-r--r--src/mainboard/intel/adlrvp/include/baseboard/variants.h3
-rw-r--r--src/mainboard/intel/adlrvp/mainboard.c3
-rw-r--r--src/mainboard/intel/adlrvp/memory.c3
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c3
4 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index af641488c9..9a94db2c7a 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -13,7 +13,8 @@ enum adl_boardid {
ADL_P_LP4_1 = 0x10,
ADL_P_LP4_2 = 0x11,
/* ADL-P DDR5 RVPs */
- ADL_P_DDR5 = 0x12,
+ ADL_P_DDR5_1 = 0x12,
+ ADL_P_DDR5_2 = 0x16,
/* ADL-P LPDDR5 RVP */
ADL_P_LP5_1 = 0x13,
ADL_P_LP5_2 = 0x17,
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 0ab80d2313..eb86773ca0 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -47,7 +47,8 @@ const char *mainboard_vbt_filename(void)
case ADL_P_LP5_1:
case ADL_P_LP5_2:
return "vbt_adlrvp_lp5.bin";
- case ADL_P_DDR5:
+ case ADL_P_DDR5_1:
+ case ADL_P_DDR5_2:
return "vbt_adlrvp_ddr5.bin";
default:
return "vbt.bin";
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 29eb74497d..353cf4eff8 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -300,7 +300,8 @@ const struct mb_cfg *variant_memory_params(void)
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
return &ddr4_mem_config;
- case ADL_P_DDR5:
+ case ADL_P_DDR5_1:
+ case ADL_P_DDR5_2:
return &ddr5_mem_config;
case ADL_P_LP5_1:
case ADL_P_LP5_2:
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 2c611250a5..9fff25723e 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -52,7 +52,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
switch (board_id) {
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
- case ADL_P_DDR5:
+ case ADL_P_DDR5_1:
+ case ADL_P_DDR5_2:
memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated);
break;
case ADL_P_LP4_1: