diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/gpio.asl | 144 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/soc_int.asl | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 3 |
3 files changed, 148 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl new file mode 100644 index 0000000000..4bf04428eb --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> + +scope (\_SB) { + + Device (GPO0) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTH, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO1) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO2) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_WEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO3) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_SOUTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } +} diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 7db23ee0d7..c7259d0d7c 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -24,6 +24,7 @@ #define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ #define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ #define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 16 #define NPK_INT 16 #define PIRQA_INT 16 #define PIRQB_INT 17 diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 46d701328a..0584439a2a 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,3 +20,6 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl" |