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-rw-r--r--src/soc/intel/alderlake/Kconfig6
-rw-r--r--src/soc/intel/alderlake/acpi/tcss.asl4
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_dma.asl12
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_pcierp.asl12
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_xhci.asl8
-rw-r--r--src/soc/intel/alderlake/fsp_params.c2
-rw-r--r--src/soc/intel/tigerlake/Kconfig6
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss.asl4
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_dma.asl12
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_pcierp.asl12
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_xhci.asl8
11 files changed, 49 insertions, 37 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 24dac49937..9c5868b0d6 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -326,6 +326,12 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 8
+config SOC_INTEL_ALDERLAKE_S3
+ bool
+ default n
+ help
+ Select if using S3 instead of S0ix to disable D3Cold.
+
config ENABLE_SATA_TEST_MODE
bool "Enable test mode for SATA margining"
default n
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 5c95997f57..1f626fc7d3 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -583,7 +583,7 @@ Scope (\_SB.PCI0)
}
}
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
/*
* TCSS xHCI device
diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl
index ca47bd0ec9..1483c0b5ac 100644
--- a/src/soc/intel/alderlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl
@@ -28,16 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Return (0x04)
#else
Return (0x03)
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR0)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -49,12 +49,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR3)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -66,7 +66,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
/*
diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index 6dbde46f49..4f1eec5d2c 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Return (0x4)
#else
Return (0x3)
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR0)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR3)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
/*
diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
index ddc5a6665d..c0dc141530 100644
--- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Return (0x4)
#else
Return (0x3)
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
/*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
/*
* XHCI controller _DSM method
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index cb3e182bab..4117c2215a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
/* D3Hot and D3Cold for TCSS */
s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
- s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
+ s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable;
s_cfg->UsbTcPortEn = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index f59d507f6d..915145085b 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -205,6 +205,12 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 6
+config SOC_INTEL_TIGERLAKE_S3
+ bool
+ default n
+ help
+ Select if using S3 instead of S0ix to disable D3Cold
+
config SOC_INTEL_UART_DEV_MAX
int
default 3
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 98337a3e5e..be9d306f6e 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -676,7 +676,7 @@ Scope (\_SB.PCI0)
}
}
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -787,7 +787,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
/*
* TCSS xHCI device
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index bbb0b6a1ad..3c19ef621e 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x04)
#else
Return (0x03)
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
}
/*
@@ -40,7 +40,7 @@ Method (_S0W, 0x0)
*/
Method (_PR0)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -52,12 +52,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
}
Method (_PR3)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -69,7 +69,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
}
/*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index 6dbde46f49..fda58e70cf 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x4)
#else
Return (0x3)
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR0)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
}
Method (_PR3)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
}
/*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
index ddc5a6665d..a3b8c8faf7 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x4)
#else
Return (0x3)
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
}
/*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_TIGERLAKE_S3
/*
* XHCI controller _DSM method
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 05:14:01 +0000