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-rw-r--r--src/soc/amd/sabrina/psp_verstage/svc.c112
-rw-r--r--src/soc/amd/sabrina/psp_verstage/svc.h86
-rw-r--r--src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h63
3 files changed, 220 insertions, 41 deletions
diff --git a/src/soc/amd/sabrina/psp_verstage/svc.c b/src/soc/amd/sabrina/psp_verstage/svc.c
index bf1a106239..370481c018 100644
--- a/src/soc/amd/sabrina/psp_verstage/svc.c
+++ b/src/soc/amd/sabrina/psp_verstage/svc.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Check if this is still correct */
-
#include "svc.h"
#include <assert.h>
#include <bl_uapp/bl_syscall_public.h>
#include <psp_verstage.h>
#include <stddef.h>
+#include <string.h>
void svc_exit(uint32_t status)
{
@@ -18,33 +17,52 @@ void svc_exit(uint32_t status)
void svc_debug_print(const char *string)
{
uint32_t unused = 0;
- SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused);
+ struct cmd_param_debug param = {
+ .debug_buffer = (char *)string,
+ .debug_buffer_len = strlen(string),
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT, (void *)&param, unused);
}
void svc_debug_print_ex(uint32_t dword0,
uint32_t dword1, uint32_t dword2, uint32_t dword3)
{
uint32_t unused = 0;
- SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused);
+ struct cmd_param_debug_ex param = {
+ .word0 = dword0,
+ .word1 = dword1,
+ .word2 = dword2,
+ .word3 = dword3,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT_EX, (void *)&param, unused);
}
uint32_t svc_get_boot_mode(uint32_t *boot_mode)
{
uint32_t retval = 0;
- SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval);
+ struct cmd_param_get_boot_mode param = {
+ .ptr_boot_mode = boot_mode,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_BOOT_MODE, (void *)&param, retval);
return retval;
}
void svc_delay_in_usec(uint32_t delay)
{
uint32_t unused = 0;
- SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused);
+ struct cmd_param_delay_in_micro_second param = {
+ .delay = delay,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DELAY_IN_MICRO_SECONDS, (void *)&param, unused);
}
uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info)
{
uint32_t retval = 0;
- SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval);
+ struct cmd_param_spirom_info param = {
+ .ptr_spirom_info = spi_rom_info,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_SPI_INFO, (void *)&param, retval);
return retval;
}
@@ -52,18 +70,26 @@ uint32_t svc_map_fch_dev(enum fch_io_device io_device,
uint32_t arg1, uint32_t arg2, void **io_device_axi_addr)
{
uint32_t retval = 0;
+ struct cmd_param_map_fch_io_device param = {
+ .io_device = io_device,
+ .arg1 = arg1,
+ .arg2 = arg2,
+ .pptr_io_device_addr_axi = io_device_axi_addr,
+ };
assert(io_device < FCH_IO_DEVICE_END);
- SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2,
- (uint32_t)io_device_axi_addr, retval);
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_FCH_IO_DEVICE, (void *)&param, retval);
return retval;
}
uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr)
{
uint32_t retval = 0;
+ struct cmd_param_unmap_fch_io_device param = {
+ .io_device = io_device,
+ .ptr_io_device_addr_axi = io_device_axi_addr,
+ };
assert(io_device < FCH_IO_DEVICE_END);
- SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device,
- (uint32_t)io_device_axi_addr, retval);
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_FCH_IO_DEVICE, (void *)&param, retval);
return retval;
}
@@ -71,15 +97,22 @@ uint32_t svc_map_spi_rom(void *spi_rom_addr,
uint32_t size, void **spi_rom_axi_addr)
{
uint32_t retval = 0;
- SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size,
- (uint32_t)spi_rom_axi_addr, retval);
+ struct cmd_param_map_spirom param = {
+ .spirom_addr = (uintptr_t)spi_rom_addr,
+ .size = size,
+ .ppspirom_addr_axi = spi_rom_axi_addr,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_SPIROM_DEVICE, (void *)&param, retval);
return retval;
}
uint32_t svc_unmap_spi_rom(void *spi_rom_addr)
{
uint32_t retval = 0;
- SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval);
+ struct cmd_param_unmap_spirom param = {
+ .ptr_spirom_addr_axi = spi_rom_addr,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_SPIROM_DEVICE, (void *)&param, retval);
return retval;
}
@@ -87,51 +120,86 @@ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset,
uint32_t *bios_dir_offset)
{
uint32_t retval = 0;
- SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset,
- (uint32_t)bios_dir_offset, retval);
+ struct cmd_param_psp_update param = {
+ .ptr_psp_dir_addr = psp_dir_offset,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UPDATE_PSP_BIOS_DIR, (void *)&param, retval);
return retval;
}
uint32_t svc_save_uapp_data(void *address, uint32_t size)
{
uint32_t retval = 0;
- SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval);
+ struct cmd_param_copy_data_from_uapp param = {
+ .address = (uintptr_t)address,
+ .size = size,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_COPY_DATA_FROM_UAPP, (void *)&param, retval);
return retval;
}
uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value)
{
unsigned int retval = 0;
+ struct cmd_param_read_timer_val param = {
+ .timer_type = type,
+ .ptr_counter_value = counter_value,
+ };
assert(type < PSP_TIMER_TYPE_MAX);
- SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval);
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_READ_TIMER_VAL, (void *)&param, retval);
return retval;
}
uint32_t svc_reset_system(enum reset_type reset_type)
{
unsigned int retval = 0;
+ struct cmd_param_reset_system param = {
+ .reset_type = reset_type,
+ };
assert(reset_type < RESET_TYPE_MAX);
- SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval);
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_RESET_SYSTEM, (void *)&param, retval);
return retval;
}
uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode)
{
uint32_t retval = 0;
- SVC_CALL2(SVC_SHA, sha_op, sha_mode, retval);
+ struct cmd_param_sha param = {
+ .ptr_sha_op = sha_op,
+ .sha_mode = sha_mode,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SHA, (void *)&param, retval);
return retval;
}
uint32_t svc_modexp(struct mod_exp_params *mod_exp_param)
{
uint32_t retval = 0;
- SVC_CALL1(SVC_MODEXP, mod_exp_param, retval);
+ struct cmd_param_modexp param = {
+ .ptr_modexp = mod_exp_param,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)&param, retval);
return retval;
}
uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size)
{
uint32_t retval = 0;
- SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval);
+ struct cmd_param_ccp_dma param = {
+ .spi_offset = spi_rom_offset,
+ .dst_addr = (uintptr_t)dest,
+ .size = size,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_CCP_DMA, (void *)&param, retval);
+ return retval;
+}
+
+uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode)
+{
+ uint32_t retval = 0;
+ struct cmd_param_set_platform_boot_mode param = {
+ .boot_mode = boot_mode,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_PLATFORM_BOOT_MODE, (void *)&param, retval);
return retval;
}
diff --git a/src/soc/amd/sabrina/psp_verstage/svc.h b/src/soc/amd/sabrina/psp_verstage/svc.h
index 86e533a88d..40dbc3e00d 100644
--- a/src/soc/amd/sabrina/psp_verstage/svc.h
+++ b/src/soc/amd/sabrina/psp_verstage/svc.h
@@ -5,6 +5,9 @@
#ifndef PSP_VERSTAGE_SVC_H
#define PSP_VERSTAGE_SVC_H
+#include <bl_uapp/bl_syscall_public.h>
+#include <types.h>
+
#define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \
__asm__ __volatile__ ( \
"mov r0, %[reg0]\n\t" \
@@ -56,4 +59,87 @@
: [id] "I" (SVC_ID) /* input(s) */ \
: "memory", "cc" /* list of clobbered registers */)
+struct cmd_param_sha {
+ struct sha_generic_data *ptr_sha_op;
+ enum sha_operation_mode sha_mode;
+};
+
+struct cmd_param_debug {
+ char *debug_buffer;
+ uint32_t debug_buffer_len;
+};
+
+struct cmd_param_debug_ex {
+ uint32_t word0;
+ uint32_t word1;
+ uint32_t word2;
+ uint32_t word3;
+};
+
+struct cmd_param_modexp {
+ struct mod_exp_params *ptr_modexp;
+};
+
+struct cmd_param_psp_update {
+ unsigned int *ptr_psp_dir_addr;
+};
+
+struct cmd_param_spirom_info {
+ struct spirom_info *ptr_spirom_info;
+};
+
+struct cmd_param_map_spirom {
+ unsigned int spirom_addr;
+ unsigned int size;
+ void **ppspirom_addr_axi;
+};
+
+struct cmd_param_unmap_spirom {
+ void *ptr_spirom_addr_axi;
+};
+
+struct cmd_param_read_timer_val {
+ enum psp_timer_type timer_type;
+ uint64_t *ptr_counter_value;
+};
+
+struct cmd_param_delay_in_micro_second {
+ uint32_t delay;
+};
+
+struct cmd_param_reset_system {
+ enum reset_type reset_type;
+};
+
+struct cmd_param_get_boot_mode {
+ unsigned int *ptr_boot_mode;
+};
+
+struct cmd_param_copy_data_from_uapp {
+ unsigned int address;
+ unsigned int size;
+};
+
+struct cmd_param_map_fch_io_device {
+ enum fch_io_device io_device;
+ unsigned int arg1;
+ unsigned int arg2;
+ void **pptr_io_device_addr_axi;
+};
+
+struct cmd_param_unmap_fch_io_device {
+ enum fch_io_device io_device;
+ void *ptr_io_device_addr_axi;
+};
+
+struct cmd_param_ccp_dma {
+ uint32_t spi_offset;
+ uint32_t dst_addr;
+ uint32_t size;
+};
+
+struct cmd_param_set_platform_boot_mode {
+ uint32_t boot_mode;
+};
+
#endif /* PSP_VERSTAGE_SVC_H */
diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h
index 06e9defea7..48c35e54ac 100644
--- a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h
+++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h
@@ -32,24 +32,29 @@
#include <stdint.h>
-#define SVC_EXIT 0x00
-#define SVC_ENTER 0x02
-#define SVC_DEBUG_PRINT 0x06
-#define SVC_MODEXP 0x0C
-#define SVC_DEBUG_PRINT_EX 0x1A
-#define SVC_GET_BOOT_MODE 0x1C
-#define SVC_DELAY_IN_MICRO_SECONDS 0x2F
-#define SVC_GET_SPI_INFO 0x60
-#define SVC_MAP_SPIROM_DEVICE 0x61
-#define SVC_UNMAP_SPIROM_DEVICE 0x62
-#define SVC_MAP_FCH_IO_DEVICE 0x63
-#define SVC_UNMAP_FCH_IO_DEVICE 0x64
-#define SVC_UPDATE_PSP_BIOS_DIR 0x65
-#define SVC_COPY_DATA_FROM_UAPP 0x66
-#define SVC_RESET_SYSTEM 0x67
-#define SVC_READ_TIMER_VAL 0x68
-#define SVC_SHA 0x69
-#define SVC_CCP_DMA 0x6A
+#define SVC_EXIT 0x00
+#define SVC_ENTER 0x02
+#define SVC_VERSTAGE_CMD 0x3A
+
+enum verstage_cmd_id {
+ CMD_SHA = 1,
+ CMD_MODEXP,
+ CMD_DEBUG_PRINT,
+ CMD_DEBUG_PRINT_EX,
+ CMD_UPDATE_PSP_BIOS_DIR,
+ CMD_GET_SPI_INFO,
+ CMD_MAP_SPIROM_DEVICE,
+ CMD_UNMAP_SPIROM_DEVICE,
+ CMD_READ_TIMER_VAL,
+ CMD_DELAY_IN_MICRO_SECONDS,
+ CMD_RESET_SYSTEM,
+ CMD_GET_BOOT_MODE,
+ CMD_COPY_DATA_FROM_UAPP,
+ CMD_MAP_FCH_IO_DEVICE,
+ CMD_UNMAP_FCH_IO_DEVICE,
+ CMD_CCP_DMA,
+ CMD_SET_PLATFORM_BOOT_MODE,
+};
struct mod_exp_params {
char *pExponent; // Exponent address
@@ -86,7 +91,6 @@ enum fch_io_device {
FCH_IO_DEVICE_MISC,
FCH_IO_DEVICE_AOAC,
FCH_IO_DEVICE_IOPORT,
-
FCH_IO_DEVICE_END,
};
@@ -136,6 +140,19 @@ struct sha_generic_data {
};
/*
+ * This is state that PSP manages internally.
+ * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_NORMAL in verstage.
+ */
+enum chrome_platform_boot_mode
+{
+ NON_CHROME_BOOK_BOOT_MODE = 0x0,
+ CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1,
+ CHROME_BOOK_BOOT_MODE_NORMAL = 0x2,
+ CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3,
+ CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check
+};
+
+/*
* Exit to the main Boot Loader. This does not return back to user application.
*
* Parameters:
@@ -313,6 +330,14 @@ uint32_t svc_modexp(struct mod_exp_params *mod_exp_param);
*/
uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size);
+/*
+ * Get the Platform boot mode from verstage. Normal or developer
+ *
+ * Parameters:
+ * - boot mode
+ -----------------------------------------------------------------------------*/
+uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode);
+
/* C entry point for the Bootloader Userspace Application */
void Main(void);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 18:49:30 +0000