diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pcr_ids.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pnpconfig.h | 776 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pnpconfig.c | 67 |
5 files changed, 860 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5fc07ae6bb..60f4ee37a9 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -60,6 +60,7 @@ ramstage-y += nhlt.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += pmutil.c +ramstage-y += pnpconfig.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += xdci.c diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index eaa932a7de..92e814b622 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -30,6 +30,12 @@ #define CLKREQ_DISABLED 0xf #define APOLLOLAKE_I2C_DEV_MAX 8 +enum pnp_settings { + PNP_PERF, + PNP_POWER, + PNP_PERF_POWER, +}; + struct soc_intel_apollolake_config { /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has @@ -133,6 +139,12 @@ struct soc_intel_apollolake_config { * (1) set sgx_enable = 1 * (2) set PrmrrSize to supported size */ uint8_t sgx_enable; + + /* Select PNP Settings. + * (0) Performance, + * (1) Power + * (2) Power & Performance */ + enum pnp_settings pnp_settings; }; typedef struct soc_intel_apollolake_config config_t; diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index ca5cf8427d..f8166932db 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -32,4 +32,8 @@ #define PID_ITSS 0xD0 #define PID_RTC 0xD1 +#define PID_AUNIT 0x4d +#define PID_BUNIT 0x4c +#define PID_TUNIT 0x52 + #endif /* SOC_INTEL_APL_PCR_H */ diff --git a/src/soc/intel/apollolake/include/soc/pnpconfig.h b/src/soc/intel/apollolake/include/soc/pnpconfig.h new file mode 100644 index 0000000000..e592e86ec7 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pnpconfig.h @@ -0,0 +1,776 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _SOC_APOLLOLAKE_PNPCONFIG_H_ +#define _SOC_APOLLOLAKE_PNPCONFIG_H_ + +#include <soc/pcr_ids.h> + +#define MAKE_MASK_INCLUSIVE(msb) MAKE_MASK(msb+1) + +#define MAKE_MASK(msb) (uint32_t)((1ULL << (msb)) - 1) + +#define MASK_VAL(msb, lsb, val) \ + ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) + +struct pnpconfig { + int msgport; + uint32_t msgregaddr; + uint32_t mask; + uint32_t value; +}; + +#define AUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(23, 16, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(7, 0, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(23, 16, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(31, 24, 0x0) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.P */ \ + { PID_AUNIT, 0x6444, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.NP */ \ + { PID_AUNIT, 0x6444, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.C */ \ + { PID_AUNIT, 0x6444, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(7, 0, 0x8) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(15, 8, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(23, 16, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(31, 24, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(7, 0, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(15, 8, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(23, 16, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(31, 24, 0xff) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_1_DISABLED */ \ + { PID_AUNIT, 0x6450, MASK_VAL(0, 0, 0x0) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.HVM_MODE */ \ + { PID_AUNIT, 0x6450, MASK_VAL(1, 1, 0x0) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.INTERLEAVE_MODE */ \ + { PID_AUNIT, 0x6450, MASK_VAL(3, 2, 0x2) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_HASH_MASK */ \ + { PID_AUNIT, 0x6450, MASK_VAL(19, 6, 0x9) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.CH_HASH_MASK */ \ + { PID_AUNIT, 0x6454, MASK_VAL(19, 6, 0x36) }, \ + /* A_CR_CHAP_SLCT1_MCHBAR.CHID_X_CNT_UPTXN */ \ + { PID_AUNIT, 0x6484, MASK_VAL(7, 0, 0xff) }, \ + /* A_CR_CHAP_SLCT1_MCHBAR.CHID_Y_CNT_UPTXN */ \ + { PID_AUNIT, 0x6484, MASK_VAL(23, 16, 0xff) } + +#define AUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(23, 16, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(7, 0, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(23, 16, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(31, 24, 0x0) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.P */ \ + { PID_AUNIT, 0x6444, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.NP */ \ + { PID_AUNIT, 0x6444, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.C */ \ + { PID_AUNIT, 0x6444, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(7, 0, 0x8) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(15, 8, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(23, 16, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(31, 24, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(7, 0, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(15, 8, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(23, 16, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(31, 24, 0xff) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_1_DISABLED */ \ + { PID_AUNIT, 0x6450, MASK_VAL(0, 0, 0x0) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.HVM_MODE */ \ + { PID_AUNIT, 0x6450, MASK_VAL(1, 1, 0x0) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.INTERLEAVE_MODE */ \ + { PID_AUNIT, 0x6450, MASK_VAL(3, 2, 0x2) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_HASH_MASK */ \ + { PID_AUNIT, 0x6450, MASK_VAL(19, 6, 0x9) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.CH_HASH_MASK */ \ + { PID_AUNIT, 0x6454, MASK_VAL(19, 6, 0x36) }, \ + /* A_CR_CHAP_SLCT1_MCHBAR.CHID_X_CNT_UPTXN */ \ + { PID_AUNIT, 0x6484, MASK_VAL(7, 0, 0xff) }, \ + /* A_CR_CHAP_SLCT1_MCHBAR.CHID_Y_CNT_UPTXN */ \ + { PID_AUNIT, 0x6484, MASK_VAL(23, 16, 0xff) } + +#define AUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(23, 16, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6430, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(7, 0, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_P_1_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x6434, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6438, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_N_1_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x643c, MASK_VAL(31, 24, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(23, 16, 0x0) }, \ + /* A_CR_CRDARB_GCNT_DEV_C_0_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6440, MASK_VAL(31, 24, 0x0) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.P */ \ + { PID_AUNIT, 0x6444, MASK_VAL(7, 0, 0x1) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.NP */ \ + { PID_AUNIT, 0x6444, MASK_VAL(15, 8, 0x1) }, \ + /* A_CR_CRDARB_GCNT_CLS_MCHBAR.C */ \ + { PID_AUNIT, 0x6444, MASK_VAL(23, 16, 0x1) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID0 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(7, 0, 0x8) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID1 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(15, 8, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID2 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(23, 16, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH0_3_MCHBAR.CHID3 */ \ + { PID_AUNIT, 0x6448, MASK_VAL(31, 24, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID4 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(7, 0, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID5 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(15, 8, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID6 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(23, 16, 0xff) }, \ + /* A_CR_GZLQ_LIMIT_CH4_7_MCHBAR.CHID7 */ \ + { PID_AUNIT, 0x644c, MASK_VAL(31, 24, 0xff) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_1_DISABLED */ \ + { PID_AUNIT, 0x6450, MASK_VAL(0, 0, 0x0) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.HVM_MODE */ \ + { PID_AUNIT, 0x6450, MASK_VAL(1, 1, 0x0) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.INTERLEAVE_MODE */ \ + { PID_AUNIT, 0x6450, MASK_VAL(3, 2, 0x2) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.SLICE_HASH_MASK */ \ + { PID_AUNIT, 0x6450, MASK_VAL(19, 6, 0x9) }, \ + /* A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR.CH_HASH_MASK */ \ + { PID_AUNIT, 0x6454, MASK_VAL(19, 6, 0x36) }, \ + /* A_CR_CHAP_SLCT1_MCHBAR.CHID_X_CNT_UPTXN */ \ + { PID_AUNIT, 0x6484, MASK_VAL(7, 0, 0xff) }, \ + /* A_CR_CHAP_SLCT1_MCHBAR.CHID_Y_CNT_UPTXN */ \ + { PID_AUNIT, 0x6484, MASK_VAL(23, 16, 0xff) } + +#define BUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ + /* B_CR_BARBCTRL0.AGENT0_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(5, 0, 0x8) }, \ + /* B_CR_BARBCTRL0.AGENT1_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(13, 8, 0x8) }, \ + /* B_CR_BARBCTRL0.AGENT2_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(21, 16, 0x8) }, \ + /* B_CR_BARBCTRL0.AGENT3_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(29, 24, 0x8) }, \ + /* B_CR_BARBCTRL1.AGENT4_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(5, 0, 0x8) }, \ + /* B_CR_BARBCTRL1.AGENT5_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(13, 8, 0x8) }, \ + /* B_CR_BARBCTRL1.AGENT6_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(21, 16, 0x8) }, \ + /* B_CR_BARBCTRL1.AGENT7_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(29, 24, 0x8) }, \ + /* B_CR_BSCHWT0.AGENT0_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(5, 0, 0x8) }, \ + /* B_CR_BSCHWT0.AGENT1_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(13, 8, 0x8) }, \ + /* B_CR_BSCHWT0.AGENT2_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(21, 16, 0x8) }, \ + /* B_CR_BSCHWT0.AGENT3_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(29, 24, 0x8) }, \ + /* B_CR_BSCHWT1.AGENT4_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(5, 0, 0x8) }, \ + /* B_CR_BSCHWT1.AGENT5_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(13, 8, 0x8) }, \ + /* B_CR_BSCHWT1.AGENT6_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(21, 16, 0x8) }, \ + /* B_CR_BSCHWT1.AGENT7_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(29, 24, 0x8) }, \ + /* B_CR_BSCHWT2.AGENT8_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(5, 0, 0x8) }, \ + /* B_CR_BSCHWT2.AGENT9_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(13, 8, 0x8) }, \ + /* B_CR_BSCHWT2.AGENT10_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(21, 16, 0x8) }, \ + /* B_CR_BSCHWT2.AGENT11_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(29, 24, 0x8) }, \ + /* B_CR_BSCHWT3.AGENT12_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(5, 0, 0x8) }, \ + /* B_CR_BSCHWT3.AGENT13_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(13, 8, 0x8) }, \ + /* B_CR_BSCHWT3.AGENT14_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(21, 16, 0x8) }, \ + /* B_CR_BSCHWT3.AGENT15_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(29, 24, 0x8) }, \ + /* B_CR_BWFLUSH.DIRTY_HWM */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(7, 0, 0x1b) }, \ + /* B_CR_BWFLUSH.DIRTY_LWM */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(15, 8, 0x0) }, \ + /* B_CR_BWFLUSH.FLUSH_THRESHOLD */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(31, 24, 0x27) }, \ + /* B_CR_BFLWT.READ_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(5, 0, 0x1) }, \ + /* B_CR_BFLWT.WRITE_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(13, 8, 0x1) }, \ + /* B_CR_BFLWT.DISABLE_FLUSH_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(31, 31, 0x0) }, \ + /* B_CR_BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(5, 0, 0xf) }, \ + /* B_CR_BISOCWT.ISOC_REQUEST_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(13, 8, 0x3f) }, \ + /* B_CR_BISOCWT.ENABLE_ISOC_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(31, 31, 0x1) }, \ + /* B_CR_BCTRL2.DIRTY_STALL */ \ + { PID_BUNIT, 0x6d70, MASK_VAL(0, 0, 0x0) } + +#define BUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ + /* B_CR_BARBCTRL0.AGENT0_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BARBCTRL0.AGENT1_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BARBCTRL0.AGENT2_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BARBCTRL0.AGENT3_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT4_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT5_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT6_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT7_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT0_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT1_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT2_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT3_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT4_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT5_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT6_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT7_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT8_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT9_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT10_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT11_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT12_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT13_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT14_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT15_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BWFLUSH.DIRTY_HWM */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(7, 0, 0x0) }, \ + /* B_CR_BWFLUSH.DIRTY_LWM */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(15, 8, 0x0) }, \ + /* B_CR_BWFLUSH.FLUSH_THRESHOLD */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(31, 24, 0x0) }, \ + /* B_CR_BFLWT.READ_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(5, 0, 0x0) }, \ + /* B_CR_BFLWT.WRITE_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(13, 8, 0x0) }, \ + /* B_CR_BFLWT.DISABLE_FLUSH_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(31, 31, 0x0) }, \ + /* B_CR_BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(5, 0, 0x0) }, \ + /* B_CR_BISOCWT.ISOC_REQUEST_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(13, 8, 0x0) }, \ + /* B_CR_BISOCWT.ENABLE_ISOC_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(31, 31, 0x0) }, \ + /* B_CR_BCTRL2.DIRTY_STALL */ \ + { PID_BUNIT, 0x6d70, MASK_VAL(0, 0, 0x0) } + +#define BUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ + /* B_CR_BARBCTRL0.AGENT0_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BARBCTRL0.AGENT1_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BARBCTRL0.AGENT2_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BARBCTRL0.AGENT3_WEIGHT */ \ + { PID_BUNIT, 0x6d4c, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT4_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT5_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT6_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BARBCTRL1.AGENT7_WEIGHT */ \ + { PID_BUNIT, 0x6d50, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT0_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT1_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT2_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT0.AGENT3_WEIGHT */ \ + { PID_BUNIT, 0x6d54, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT4_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT5_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT6_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT1.AGENT7_WEIGHT */ \ + { PID_BUNIT, 0x6d58, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT8_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT9_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT10_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT2.AGENT11_WEIGHT */ \ + { PID_BUNIT, 0x6d5c, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT12_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(5, 0, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT13_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(13, 8, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT14_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(21, 16, 0x4) }, \ + /* B_CR_BSCHWT3.AGENT15_WEIGHT */ \ + { PID_BUNIT, 0x6d60, MASK_VAL(29, 24, 0x4) }, \ + /* B_CR_BWFLUSH.DIRTY_HWM */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(7, 0, 0x0) }, \ + /* B_CR_BWFLUSH.DIRTY_LWM */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(15, 8, 0x0) }, \ + /* B_CR_BWFLUSH.FLUSH_THRESHOLD */ \ + { PID_BUNIT, 0x6d64, MASK_VAL(31, 24, 0x0) }, \ + /* B_CR_BFLWT.READ_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(5, 0, 0x0) }, \ + /* B_CR_BFLWT.WRITE_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(13, 8, 0x0) }, \ + /* B_CR_BFLWT.DISABLE_FLUSH_WEIGHTS */ \ + { PID_BUNIT, 0x6d68, MASK_VAL(31, 31, 0x0) }, \ + /* B_CR_BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(5, 0, 0x0) }, \ + /* B_CR_BISOCWT.ISOC_REQUEST_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(13, 8, 0x0) }, \ + /* B_CR_BISOCWT.ENABLE_ISOC_WEIGHTS */ \ + { PID_BUNIT, 0x6d6c, MASK_VAL(31, 31, 0x0) }, \ + /* B_CR_BCTRL2.DIRTY_STALL */ \ + { PID_BUNIT, 0x6d70, MASK_VAL(0, 0, 0x0) } + +#define TUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ + /* CTL_MCHBAR.ALWAYS_SNP_PII2 */ \ + { PID_TUNIT, 0x7810, MASK_VAL(0, 0, 0x0) }, \ + /* CTL_MCHBAR.OUTSTND_SNP */ \ + { PID_TUNIT, 0x7810, MASK_VAL(1, 1, 0x0) }, \ + /* CTL_MCHBAR.DIS_LIVE_BRAM_BYP_IDI */ \ + { PID_TUNIT, 0x7810, MASK_VAL(2, 2, 0x0) }, \ + /* CTL_MCHBAR.ALWAYS_SNP_IDI */ \ + { PID_TUNIT, 0x7810, MASK_VAL(3, 3, 0x0) }, \ + /* CTL_MCHBAR.SNPINV */ \ + { PID_TUNIT, 0x7810, MASK_VAL(7, 7, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ + { PID_TUNIT, 0x7810, MASK_VAL(18, 18, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ + { PID_TUNIT, 0x7810, MASK_VAL(19, 19, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_SNOOPING_GT */ \ + { PID_TUNIT, 0x7810, MASK_VAL(20, 20, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(0, 0, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(1, 1, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(2, 2, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(3, 3, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(4, 4, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(5, 5, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(6, 6, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(7, 7, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(0, 0, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(1, 1, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(2, 2, 0x0) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(3, 3, 0x0) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(4, 4, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(5, 5, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(6, 6, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(7, 7, 0x1) }, \ + /* T_CR_CTL.ALWAYS_SNP_PII2 */ \ + { PID_TUNIT, 0x523c, MASK_VAL(0, 0, 0x0) }, \ + /* T_CR_CTL.DIS_LIVE_BRAM_BYP_IDI */ \ + { PID_TUNIT, 0x523c, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_CTL.ALWAYS_SNP_IDI */ \ + { PID_TUNIT, 0x523c, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ + { PID_TUNIT, 0x523c, MASK_VAL(18, 18, 0x0) }, \ + /* T_CR_CTL.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ + { PID_TUNIT, 0x523c, MASK_VAL(19, 19, 0x0) }, \ + /* T_CR_CTL.DISABLE_SNOOPING_GT */ \ + { PID_TUNIT, 0x523c, MASK_VAL(20, 20, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(0, 0, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(1, 1, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(4, 4, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(5, 5, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(6, 6, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(7, 7, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(0, 0, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(1, 1, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(4, 4, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(5, 5, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(6, 6, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(7, 7, 0x1) } + +#define TUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ + /* CTL_MCHBAR.ALWAYS_SNP_PII2 */ \ + { PID_TUNIT, 0x7810, MASK_VAL(0, 0, 0x0) }, \ + /* CTL_MCHBAR.OUTSTND_SNP */ \ + { PID_TUNIT, 0x7810, MASK_VAL(1, 1, 0x0) }, \ + /* CTL_MCHBAR.DIS_LIVE_BRAM_BYP_IDI */ \ + { PID_TUNIT, 0x7810, MASK_VAL(2, 2, 0x0) }, \ + /* CTL_MCHBAR.ALWAYS_SNP_IDI */ \ + { PID_TUNIT, 0x7810, MASK_VAL(3, 3, 0x0) }, \ + /* CTL_MCHBAR.SNPINV */ \ + { PID_TUNIT, 0x7810, MASK_VAL(7, 7, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ + { PID_TUNIT, 0x7810, MASK_VAL(18, 18, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ + { PID_TUNIT, 0x7810, MASK_VAL(19, 19, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_SNOOPING_GT */ \ + { PID_TUNIT, 0x7810, MASK_VAL(20, 20, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(0, 0, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(1, 1, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(2, 2, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(3, 3, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(4, 4, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(5, 5, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(6, 6, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(7, 7, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(0, 0, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(1, 1, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(2, 2, 0x0) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(3, 3, 0x0) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(4, 4, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(5, 5, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(6, 6, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(7, 7, 0x1) }, \ + /* T_CR_CTL.ALWAYS_SNP_PII2 */ \ + { PID_TUNIT, 0x523c, MASK_VAL(0, 0, 0x0) }, \ + /* T_CR_CTL.DIS_LIVE_BRAM_BYP_IDI */ \ + { PID_TUNIT, 0x523c, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_CTL.ALWAYS_SNP_IDI */ \ + { PID_TUNIT, 0x523c, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ + { PID_TUNIT, 0x523c, MASK_VAL(18, 18, 0x0) }, \ + /* T_CR_CTL.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ + { PID_TUNIT, 0x523c, MASK_VAL(19, 19, 0x0) }, \ + /* T_CR_CTL.DISABLE_SNOOPING_GT */ \ + { PID_TUNIT, 0x523c, MASK_VAL(20, 20, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(0, 0, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(1, 1, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(4, 4, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(5, 5, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(6, 6, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(7, 7, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(0, 0, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(1, 1, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(4, 4, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(5, 5, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(6, 6, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(7, 7, 0x1) } + +#define TUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ + /* CTL_MCHBAR.ALWAYS_SNP_PII2 */ \ + { PID_TUNIT, 0x7810, MASK_VAL(0, 0, 0x0) }, \ + /* CTL_MCHBAR.OUTSTND_SNP */ \ + { PID_TUNIT, 0x7810, MASK_VAL(1, 1, 0x0) }, \ + /* CTL_MCHBAR.DIS_LIVE_BRAM_BYP_IDI */ \ + { PID_TUNIT, 0x7810, MASK_VAL(2, 2, 0x0) }, \ + /* CTL_MCHBAR.ALWAYS_SNP_IDI */ \ + { PID_TUNIT, 0x7810, MASK_VAL(3, 3, 0x0) }, \ + /* CTL_MCHBAR.SNPINV */ \ + { PID_TUNIT, 0x7810, MASK_VAL(7, 7, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ + { PID_TUNIT, 0x7810, MASK_VAL(18, 18, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ + { PID_TUNIT, 0x7810, MASK_VAL(19, 19, 0x0) }, \ + /* CTL_MCHBAR.DISABLE_SNOOPING_GT */ \ + { PID_TUNIT, 0x7810, MASK_VAL(20, 20, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(0, 0, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(1, 1, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(2, 2, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(3, 3, 0x0) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(4, 4, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(5, 5, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(6, 6, 0x1) }, \ + /* VC_READ_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x781c, MASK_VAL(7, 7, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(0, 0, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(1, 1, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(2, 2, 0x0) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(3, 3, 0x0) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(4, 4, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(5, 5, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(6, 6, 0x1) }, \ + /* VC_WRITE_ORDERING_CFG_MCHBAR.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x7820, MASK_VAL(7, 7, 0x1) }, \ + /* T_CR_CTL.ALWAYS_SNP_PII2 */ \ + { PID_TUNIT, 0x523c, MASK_VAL(0, 0, 0x0) }, \ + /* T_CR_CTL.DIS_LIVE_BRAM_BYP_IDI */ \ + { PID_TUNIT, 0x523c, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_CTL.ALWAYS_SNP_IDI */ \ + { PID_TUNIT, 0x523c, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN */ \ + { PID_TUNIT, 0x523c, MASK_VAL(18, 18, 0x0) }, \ + /* T_CR_CTL.DISABLE_OPPORTUNISTIC_SLICE1_SCHEDULE */ \ + { PID_TUNIT, 0x523c, MASK_VAL(19, 19, 0x0) }, \ + /* T_CR_CTL.DISABLE_SNOOPING_GT */ \ + { PID_TUNIT, 0x523c, MASK_VAL(20, 20, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(0, 0, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(1, 1, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(4, 4, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(5, 5, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(6, 6, 0x1) }, \ + /* T_CR_VC_READ_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x5288, MASK_VAL(7, 7, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(0, 0, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC0B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(1, 1, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(2, 2, 0x0) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC1B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(3, 3, 0x0) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2A_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(4, 4, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2B_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(5, 5, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VC2C_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(6, 6, 0x1) }, \ + /* T_CR_VC_WRITE_ORDERING_CFG.UPSTREAM_VCBR_IN_ORDER */ \ + { PID_TUNIT, 0x528c, MASK_VAL(7, 7, 0x1) } + +#define VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT \ + AUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT, \ + BUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT, \ + TUNIT_VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT + +#define VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT \ + AUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT, \ + BUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT, \ + TUNIT_VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT + +#define VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT \ + AUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT, \ + BUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT, \ + TUNIT_VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT + +#endif /* _SOC_APOLLOLAKE_PNPCONFIG_H_ */ diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c new file mode 100644 index 0000000000..f9d493ed3e --- /dev/null +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include <bootstate.h> +#include <console/console.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pnpconfig.h> +#include "chip.h" + +static const struct pnpconfig perf[] = { + VALUEFORPERF_MSG_VALUES_PLATFORM_DEFAULT, +}; + +static const struct pnpconfig power[] = { + VALUEFORPOWER_MSG_VALUES_PLATFORM_DEFAULT, +}; + +static const struct pnpconfig power_perf[] = { + VALUEFORPWRPERF_MSG_VALUES_PLATFORM_DEFAULT, +}; + +static void pnp_settings(void *unused) +{ + int index; + size_t arrsize; + const struct pnpconfig *pnpconfigarr; + struct device *dev = SA_DEV_ROOT; + struct soc_intel_apollolake_config *config = dev->chip_info; + switch (config->pnp_settings) { + case PNP_PERF: + pnpconfigarr = perf; + arrsize = ARRAY_SIZE(perf); + break; + case PNP_POWER: + pnpconfigarr = power; + arrsize = ARRAY_SIZE(power); + break; + case PNP_PERF_POWER: + pnpconfigarr = power_perf; + arrsize = ARRAY_SIZE(power_perf); + break; + default: + printk(BIOS_NOTICE, "Invalid PNP settings selected"); + return; + } + + for (index = 0; index < arrsize; index++) + pcr_rmw32(pnpconfigarr[index].msgport, + pnpconfigarr[index].msgregaddr, + pnpconfigarr[index].mask, + pnpconfigarr[index].value); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pnp_settings, NULL); |