diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/ibm/e325/auto.c | 7 | ||||
| -rw-r--r-- | src/mainboard/ibm/e325/resourcemap.c | 4 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/ibm/e325/auto.c b/src/mainboard/ibm/e325/auto.c index 06fcb0ab0b..84cf6efeab 100644 --- a/src/mainboard/ibm/e325/auto.c +++ b/src/mainboard/ibm/e325/auto.c @@ -30,7 +30,7 @@ static void hard_reset(void) set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(PCI_DEV(1, 0x04, 3), 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } @@ -38,7 +38,7 @@ static void hard_reset(void) static void soft_reset(void) { set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); } static void memreset_setup(void) @@ -122,6 +122,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" +#include "mainboard/ibm/e325/resourcemap.c" @@ -172,7 +173,7 @@ static void main(void) pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - setup_default_resource_map(); + setup_ibm_e325_resource_map(); needs_reset = setup_coherent_ht_domain(); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); if (needs_reset) { diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c index 0c373deaae..efeaf6e087 100644 --- a/src/mainboard/ibm/e325/resourcemap.c +++ b/src/mainboard/ibm/e325/resourcemap.c @@ -103,7 +103,7 @@ CONF 0x3(0xffff0330): * */ -static void setup_s2885_resource_map(void) +static void setup_ibm_e325_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ @@ -355,7 +355,7 @@ static void setup_s2885_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, ff000103, + PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0xff000103, PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0, |