diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/asus/p2b/dsdt.asl | 74 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/acpi/i82371eb.asl | 86 |
2 files changed, 84 insertions, 76 deletions
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 9e7951b4b5..2c88cf692e 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -165,79 +165,7 @@ DefinitionBlock ( #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> #include <southbridge/intel/i82371eb/acpi/isabridge.asl> - /* Begin southbridge block */ - Device (PX40) - { - Name(_ADR, 0x00040000) - OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) - Field (PIRQ, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8 - } - - /* PNP Motherboard Resources */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x02) - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) - /* PIIX4E ports */ - /* Aliased DMA ports */ - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) - /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) - /* Aliased timer ports */ - IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) - IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) - IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) - }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - PMLO = \_SB.PCI0.PX43.PM00 & 0xFFFE - SBLO = \_SB.PCI0.PX43.SB00 & 0xFFFE - PMRL = PMLO - SBRL = SBLO - Return (BUF1) - } - } - #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> - } - Device (PX43) - { - Name (_ADR, 0x00040003) // _ADR: Address - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } - } - + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> #include <superio/winbond/w83977tf/acpi/superio.asl> } } diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index e0fb715a8f..17fd61d604 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -1,16 +1,67 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Declares assorted devices that falls under this southbridge. - */ #include "southbridge/intel/i82371eb/i82371eb.h" +/* Declares assorted devices that fall under this southbridge. */ +Device (PX40) +{ + Name(_ADR, 0x00040000) + OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) + Field (PIRQ, ByteAcc, NoLock, Preserve) + { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } + OperationRegion (S1XX, PCI_Config, 0xB2, 0x01) Field (S1XX, ByteAcc, NoLock, Preserve) { FXS1, 8 } + /* PNP Motherboard Resources */ + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* PM register ports */ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) + /* SMBus register ports */ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) + /* PIIX4E ports */ + /* Aliased DMA ports */ + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) + /* Aliased PIC ports */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + /* Aliased timer ports */ + IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) + IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) + IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) + }) + CreateWordField (BUF1, _Y06._MIN, PMLO) + CreateWordField (BUF1, _Y06._MAX, PMRL) + CreateWordField (BUF1, _Y07._MIN, SBLO) + CreateWordField (BUF1, _Y07._MAX, SBRL) + And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) + And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) + Store (PMLO, PMRL) + Store (SBLO, SBRL) + Return (BUF1) + } + } /* 8259-compatible Programmable Interrupt Controller */ Device (PIC) { @@ -78,3 +129,32 @@ IRQNoFlags () {13} }) } +} +Device (PX43) +{ + Name (_ADR, 0x00040003) // _ADR: Address + + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* PM register ports */ + IO (Decode16, PM_IO_BASE, PM_IO_BASE, 0x01, 0x40, ) + /* SMBus register ports */ + IO (Decode16, SMBUS_IO_BASE, SMBUS_IO_BASE, 0x01, 0x10, ) + }) + Return (BUF1) + } + + OperationRegion (IPMU, PCI_Config, PMBA, 0x02) + Field (IPMU, ByteAcc, NoLock, Preserve) + { + PM00, 16 + } + + OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) + Field (ISMB, ByteAcc, NoLock, Preserve) + { + SB00, 16 + } +} |