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-rw-r--r--src/soc/mediatek/mt8183/include/soc/rtc.h1
-rw-r--r--src/soc/mediatek/mt8183/rtc.c5
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 841a202519..1f6f06a568 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -147,6 +147,7 @@ enum {
PMIC_RG_DCXO_CW15 = 0x07AE,
PMIC_RG_DCXO_CW16 = 0x07B0,
PMIC_RG_DCXO_CW21 = 0x07BA,
+ PMIC_RG_DCXO_CW23 = 0x07BE,
PMIC_RG_DCXO_ELR0 = 0x07C4
};
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 5879088434..3bd3ab4921 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -274,9 +274,10 @@ static void dcxo_init(void)
rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
/* 26M enable control */
- /* Enable clock buffer XO_SOC, XO_CEL */
- rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
+ /* Enable clock buffer XO_SOC */
+ rtc_write(PMIC_RG_DCXO_CW00, 0x4005);
rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
+ rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
/* Load thermal coefficient */
rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);