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-rw-r--r--src/soc/intel/cannonlake/Kconfig28
1 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 1c0f1bffbe..471fe6ca78 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -8,37 +8,37 @@ if SOC_INTEL_CANNONLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
- select SOC_INTEL_COMMON_BLOCK_TIMER
- select HAVE_MONOTONIC_TIMER
- select TSC_CONSTANT_RATE
- select TSC_MONOTONIC_TIMER
- select UDELAY_TSC
- select REG_SCRIPT
+ select ARCH_VERSTAGE_X86_32
select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE
+ select HAVE_MONOTONIC_TIMER
select INTEL_CAR_NEM_ENHANCED
select PLATFORM_USES_FSP2_0
+ select REG_SCRIPT
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
- select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CPU
- select SOC_INTEL_COMMON_RESET
- select SOC_INTEL_COMMON_BLOCK_LPSS
- select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+ select SOC_INTEL_COMMON_BLOCK_GPIO
+ select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
- select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_RTC
- select SOC_INTEL_COMMON_BLOCK_CSE
- select SOC_INTEL_COMMON_BLOCK_GPIO
+ select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_SMBUS
+ select SOC_INTEL_COMMON_BLOCK_TIMER
+ select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_RESET
select SUPPORT_CPU_UCODE_IN_CBFS
+ select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
+ select UDELAY_TSC
config UART_DEBUG
bool "Enable UART debug port."