diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/cpu/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/car/exit_car.S | 3 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc | 29 |
3 files changed, 9 insertions, 31 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 86cc77194c..5941599df0 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -3,6 +3,8 @@ config SOC_AMD_COMMON_BLOCK_CAR default n help This option allows the SOC to use a standard AMD cache-as-ram (CAR) - implementation. CAR setup is built into bootblock and teardown in - romstage. If it is not used the system must implement these functions - separately. + implementation. CAR setup is built into bootblock and teardown is + in postcar. The teardown procedure does not preserve the stack so + it may not be appropriate for a romstage implementation without + additional consideration. If this option is not used, the SOC must + implement these functions separately. diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index ac36cb0e4f..f9d056e599 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -20,6 +20,7 @@ .globl chipset_teardown_car chipset_teardown_car: + pop %esp /* Disable cache */ movl %cr0, %eax @@ -33,4 +34,4 @@ chipset_teardown_car: andl $(~(CR0_CD | CR0_NW)), %eax movl %eax, %cr0 - ret + jmp *%esp diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index 92fd7e24fb..c744e47a03 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -401,16 +401,6 @@ fam15_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * -* Note: Customized for coreboot: -* A wbinvd is used to send cache to memory. The existing stack is preserved -* at its original location and additional information is preserved (e.g. -* coreboot CAR globals, heap structures, etc.). This implementation should -* NOT be used with S3 resume IF the stack/cache area is not reserved and -* over system memory. -* -* This CPU resume path doesn't use CAR, but be careful if porting to -* other CPUs. -* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -644,12 +634,7 @@ fam15_disable_stack_remote_read_exit: # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- - #-------------------------------------------------------------------------- - # Send cache to memory. Preserve stack and coreboot CAR globals. - # This shouldn't be used with S3 resume IF the stack/cache area is - # not reserved and over system memory. - #-------------------------------------------------------------------------- - wbinvd + invd # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh @@ -1289,17 +1274,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is .endm /***************************************************************************** -* AMD_DISABLE_STACK: Implementation is modified for coreboot from -* the original AMD intent. A WBINVD is used in the HOOK -* to send dirty cache contents to DRAM backing before -* disabling cache-as-ram. This is not safe for S3 resume. -* -* todo: -* * rework PI/AGESA source to set DRAM to UC to send -* writes directly to memory -* * move DCACHE_BASE or use postcar stage for teardown -* to eliminate car_migrated problem that will occur -* after wbinvd is changed back to invd +* AMD_DISABLE_STACK: * * In: * none |