diff options
Diffstat (limited to 'src')
64 files changed, 279 insertions, 347 deletions
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index ed528d1bdd..edc2996f05 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -24,6 +24,7 @@ #include <cpu/intel/microcode/microcode.c> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> #include "model_2065x.h" #else diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 670b09750e..90215a496d 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -28,6 +28,7 @@ IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/rcba.h> #else #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index b9cfa2023a..25ddb9852b 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -25,6 +25,7 @@ #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/apple/macbookair4_2/mainboard.c b/src/mainboard/apple/macbookair4_2/mainboard.c index 68e12fe003..f48b9b13a0 100644 --- a/src/mainboard/apple/macbookair4_2/mainboard.c +++ b/src/mainboard/apple/macbookair4_2/mainboard.c @@ -13,6 +13,7 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> #include <console/console.h> diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 69492462be..00a8d1f1d3 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include "northbridge/intel/sandybridge/raminit_native.h" #include <superio/smsc/sio1007/chip.h> +#include <southbridge/intel/common/rcba.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index d1fcfbca8b..590e25f110 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 5a2c935d5a..92bef2882f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -28,6 +28,7 @@ #include <superio/ite/common/ite.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c index d1fcfbca8b..590e25f110 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index a389e68f0d..283ad46dca 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -28,6 +28,7 @@ #include <superio/ite/common/ite.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 3ef4659a5a..a300ff6958 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index cbb7199b02..544bb4af6e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 507107a0f0..3b7c24279b 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 1b02163c9b..ffa2157c8f 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index c70660aee9..1eea89dea1 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index f33415741f..873718fb12 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -23,7 +23,7 @@ #include <arch/acpi.h> #include <console/console.h> #include "northbridge/intel/sandybridge/raminit_native.h" - +#include <southbridge/intel/common/rcba.h> #include "superio.h" #include "thermal.h" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 3271d630c9..24c4b564c2 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -31,6 +31,7 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 2a674a5374..bff4991810 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 0f6ffede3d..de4e9f3cb4 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -20,6 +20,7 @@ #include <device/pnp_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index b83eeaec73..83664f4ce6 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -27,6 +27,7 @@ #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" +#include <southbridge/intel/common/rcba.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 36e83a3c72..bac7288d51 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 55011cf2e2..025a0fddba 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 3f6d9f2836..0e732ee529 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -20,6 +20,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index d6e5edd92d..304f337e81 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index f8bb490323..d2f7390314 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -21,6 +21,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 961d76d267..9ccf1d3b26 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <ec/acpi/ec.h> #include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 3c723ab65e..8e8a5df30b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -39,6 +39,7 @@ #include "dock.h" #include "arch/early_variables.h" +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index a6c5793359..bdd251a708 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1a7decce59..7801d5786a 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 42b345ed81..31b8f76b01 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -37,6 +37,7 @@ #include <cbmem.h> #include "arch/early_variables.h" +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c index b36725c213..6a3a56efe5 100644 --- a/src/mainboard/roda/rv11/romstage.c +++ b/src/mainboard/roda/rv11/romstage.c @@ -14,6 +14,7 @@ */ #include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> void mainboard_rcba_config(void) diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index c7de994760..549167bbca 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -18,6 +18,7 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 131be72baf..d7ed4350b6 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,6 +32,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 13034933f8..265530c56f 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -32,6 +32,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c index 8e93ff58e1..02d2d85987 100644 --- a/src/mainboard/sapphire/pureplatinumh61/mainboard.c +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -17,6 +17,7 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/rcba.h> static void mainboard_init(device_t dev) { diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index a20a1f758b..420a956ebb 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -27,6 +27,7 @@ #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" +#include <southbridge/intel/common/rcba.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 3f55140883..319d81def1 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -25,6 +25,7 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <arch/cpu.h> +#include <southbridge/intel/common/rcba.h> #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 7a460fc054..33df32fa46 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -169,6 +169,7 @@ typedef struct { #define QUICKPATH_BUS 0xff +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> /* Everything below this line is ignored in the DSDT */ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b7b445ec86..a2ccbc36a8 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -55,6 +55,7 @@ typedef u32 device_t; #include "nehalem.h" +#include <southbridge/intel/common/rcba.h> #include "southbridge/intel/ibexpeak/me.h" #if REAL diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 2f1b790bcb..612e25b116 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> +#include <southbridge/intel/common/rcba.h> #include "sandybridge.h" static void sandybridge_setup_bars(void) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8bbfae92a0..a3b4faad1d 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -58,6 +58,7 @@ #define IOMMU_BASE2 0xfed91000ULL #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/rcba.h> /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 9c8eaf6bff..02165d6c7f 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <delay.h> #include <device/azalia_device.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 85419030b4..b3a191124b 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -15,6 +15,7 @@ #include <arch/io.h> #include <cpu/x86/tsc.h> +#include "southbridge/intel/common/rcba.h" #include "pch.h" static void store_initial_timestamp(void) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 4015495e4e..427e58c6f2 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -24,6 +24,7 @@ #include <device/pci_def.h> #include <delay.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" /* For DMI bar. */ #include "northbridge/intel/sandybridge/sandybridge.h" diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 9bd3a26e22..990ff0d874 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -17,6 +17,7 @@ #include <stdint.h> #include "pch.h" +#include <southbridge/intel/common/rcba.h> #include "northbridge/intel/sandybridge/sandybridge.h" void diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c index 140083734d..a9ecd82e54 100644 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ b/src/southbridge/intel/bd82x6x/early_spi.c @@ -19,6 +19,7 @@ #include <device/pci_ids.h> #include <device/pci_def.h> #include <delay.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #define SPI_DELAY 10 /* 10us */ diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index a5c63b617f..37df501a73 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include "pch.h" +#include <southbridge/intel/common/rcba.h> #include "cpu/intel/model_206ax/model_206ax.h" #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index fe28af0385..6b38fcd563 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7f61669cf9..4212d1abbe 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -32,6 +32,7 @@ #include <cbmem.h> #include <string.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 70ba301c38..a5c5e52458 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -39,6 +39,7 @@ # include <device/pci.h> #endif +#include <southbridge/intel/common/rcba.h> #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 2e29233a86..6463f9632a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -39,6 +39,7 @@ # include <device/pci.h> #endif +#include <southbridge/intel/common/rcba.h> #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 0b0fc3578f..73c84bbb5d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -24,6 +24,7 @@ #include <device/device.h> #include <device/pci.h> #endif +#include <southbridge/intel/common/rcba.h> #include "pch.h" #include <string.h> diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b094826336..ac2d036f37 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -45,12 +45,6 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) #define CROS_GPIO_DEVICE_NAME "CougarPoint" #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) @@ -279,73 +273,6 @@ int rtc_failure(void); /* Root Complex Register Block */ #define RCBA 0xf0 -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ -#define RPFN 0x0404 /* 32bit */ - -/* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) -/* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) -/* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) -/* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) - -#define TRSR 0x1e00 /* 8bit */ -#define TRCR 0x1e10 /* 64bit */ -#define TWDR 0x1e18 /* 64bit */ - -#define IOTR0 0x1e80 /* 64bit */ -#define IOTR1 0x1e88 /* 64bit */ -#define IOTR2 0x1e90 /* 64bit */ -#define IOTR3 0x1e98 /* 64bit */ - -#define TCTL 0x3000 /* 8bit */ #define NOINT 0 #define INTA 1 @@ -375,85 +302,9 @@ int rtc_failure(void); #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) -#define D31IP 0x3100 /* 32bit */ -#define D31IP_TTIP 24 /* Thermal Throttle Pin */ -#define D31IP_SIP2 20 /* SATA Pin 2 */ -#define D31IP_SMIP 12 /* SMBUS Pin */ -#define D31IP_SIP 8 /* SATA Pin */ -#define D30IP 0x3104 /* 32bit */ -#define D30IP_PIP 0 /* PCI Bridge Pin */ -#define D29IP 0x3108 /* 32bit */ -#define D29IP_E1P 0 /* EHCI #1 Pin */ -#define D28IP 0x310c /* 32bit */ -#define D28IP_P8IP 28 /* PCI Express Port 8 */ -#define D28IP_P7IP 24 /* PCI Express Port 7 */ -#define D28IP_P6IP 20 /* PCI Express Port 6 */ -#define D28IP_P5IP 16 /* PCI Express Port 5 */ -#define D28IP_P4IP 12 /* PCI Express Port 4 */ -#define D28IP_P3IP 8 /* PCI Express Port 3 */ -#define D28IP_P2IP 4 /* PCI Express Port 2 */ -#define D28IP_P1IP 0 /* PCI Express Port 1 */ -#define D27IP 0x3110 /* 32bit */ -#define D27IP_ZIP 0 /* HD Audio Pin */ -#define D26IP 0x3114 /* 32bit */ -#define D26IP_E2P 0 /* EHCI #2 Pin */ -#define D25IP 0x3118 /* 32bit */ -#define D25IP_LIP 0 /* GbE LAN Pin */ -#define D22IP 0x3124 /* 32bit */ -#define D22IP_KTIP 12 /* KT Pin */ -#define D22IP_IDERIP 8 /* IDE-R Pin */ -#define D22IP_MEI2IP 4 /* MEI #2 Pin */ -#define D22IP_MEI1IP 0 /* MEI #1 Pin */ -#define D20IP 0x3128 /* 32bit */ -#define D20IP_XHCIIP 0 -#define D31IR 0x3140 /* 16bit */ -#define D30IR 0x3142 /* 16bit */ -#define D29IR 0x3144 /* 16bit */ -#define D28IR 0x3146 /* 16bit */ -#define D27IR 0x3148 /* 16bit */ -#define D26IR 0x314c /* 16bit */ -#define D25IR 0x3150 /* 16bit */ -#define D22IR 0x315c /* 16bit */ -#define D20IR 0x3160 /* 16bit */ -#define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) - -#define RC 0x3400 /* 32bit */ -#define HPTC 0x3404 /* 32bit */ -#define GCS 0x3410 /* 32bit */ -#define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) -#define FD 0x3418 /* 32bit */ -#define DISPBDF 0x3424 /* 16bit */ -#define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ - -/* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) -#define PCH_DISABLE_P2P (1 << 1) -#define PCH_DISABLE_SATA1 (1 << 2) -#define PCH_DISABLE_SMBUS (1 << 3) -#define PCH_DISABLE_HD_AUDIO (1 << 4) -#define PCH_DISABLE_EHCI2 (1 << 13) -#define PCH_DISABLE_LPC (1 << 14) -#define PCH_DISABLE_EHCI1 (1 << 15) -#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) -#define PCH_DISABLE_THERMAL (1 << 24) -#define PCH_DISABLE_SATA2 (1 << 25) -#define PCH_DISABLE_XHCI (1 << 27) - -/* Function Disable 2 RCBA 0x3428 */ -#define PCH_DISABLE_KT (1 << 4) -#define PCH_DISABLE_IDER (1 << 3) -#define PCH_DISABLE_MEI2 (1 << 2) -#define PCH_DISABLE_MEI1 (1 << 1) -#define PCH_ENABLE_DBDF (1 << 0) - /* USB Port Disable Override */ #define USBPDO 0x359c /* 32bit */ /* USB Overcurrent MAP Register */ diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 34b7694dcf..1f4c157f14 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -21,6 +21,7 @@ #include <device/pci_ids.h> #include <southbridge/intel/common/pciehp.h> #include <assert.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" static void pch_pcie_pm_early(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 165acab837..bf72b5e324 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -23,6 +23,7 @@ #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 90b29c4df9..b5ce820b0f 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #include <device/pci_ehci.h> #include <arch/io.h> diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h new file mode 100644 index 0000000000..1399fdef90 --- /dev/null +++ b/src/southbridge/intel/common/rcba.h @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H +#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H + +/* + * The DnnIR registers use common RCBA offsets across these chipsets: + * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint + * + * However not all registers are in use on all of these. + */ + +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else +#define DEFAULT_RCBA 0xfed1c000 +#endif + +#ifndef __ACPI__ + +#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) +#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) +#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) + +#define RCBA_AND_OR(bits, x, and, or) \ + (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) +#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) +#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) +#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) +#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) + + +#define VCH 0x0000 /* 32bit */ +#define VCAP1 0x0004 /* 32bit */ +#define VCAP2 0x0008 /* 32bit */ +#define PVC 0x000c /* 16bit */ +#define PVS 0x000e /* 16bit */ + +#define V0CAP 0x0010 /* 32bit */ +#define V0CTL 0x0014 /* 32bit */ +#define V0STS 0x001a /* 16bit */ + +#define V1CAP 0x001c /* 32bit */ +#define V1CTL 0x0020 /* 32bit */ +#define V1STS 0x0026 /* 16bit */ + +#define RCTCL 0x0100 /* 32bit */ +#define ESD 0x0104 /* 32bit */ +#define ULD 0x0110 /* 32bit */ +#define ULBA 0x0118 /* 64bit */ + +#define RP1D 0x0120 /* 32bit */ +#define RP1BA 0x0128 /* 64bit */ +#define RP2D 0x0130 /* 32bit */ +#define RP2BA 0x0138 /* 64bit */ +#define RP3D 0x0140 /* 32bit */ +#define RP3BA 0x0148 /* 64bit */ +#define RP4D 0x0150 /* 32bit */ +#define RP4BA 0x0158 /* 64bit */ +#define HDD 0x0160 /* 32bit */ +#define HDBA 0x0168 /* 64bit */ +#define RP5D 0x0170 /* 32bit */ +#define RP5BA 0x0178 /* 64bit */ +#define RP6D 0x0180 /* 32bit */ +#define RP6BA 0x0188 /* 64bit */ + +#define RPC 0x0400 /* 32bit */ +#define RPFN 0x0404 /* 32bit */ + +/* Root Port configuratinon space hide */ +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) +/* Get the function number assigned to a Root Port */ +#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7) +/* Set the function number for a Root Port */ +#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4)) +/* Root Port function number mask */ +#define RPFN_FNMASK(port) (7 << ((port) * 4)) + +#define TRSR 0x1e00 /* 8bit */ +#define TRCR 0x1e10 /* 64bit */ +#define TWDR 0x1e18 /* 64bit */ + +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +#define TCTL 0x3000 /* 8bit */ + + +#define D31IP 0x3100 /* 32bit */ +#define D31IP_TTIP 24 /* Thermal Throttle Pin */ +#define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_SMIP 12 /* SMBUS Pin */ +#define D31IP_SIP 8 /* SATA Pin */ +#define D30IP 0x3104 /* 32bit */ +#define D30IP_PIP 0 /* PCI Bridge Pin */ +#define D29IP 0x3108 /* 32bit */ +#define D29IP_E1P 0 /* EHCI #1 Pin */ +#define D28IP 0x310c /* 32bit */ +#define D28IP_P8IP 28 /* PCI Express Port 8 */ +#define D28IP_P7IP 24 /* PCI Express Port 7 */ +#define D28IP_P6IP 20 /* PCI Express Port 6 */ +#define D28IP_P5IP 16 /* PCI Express Port 5 */ +#define D28IP_P4IP 12 /* PCI Express Port 4 */ +#define D28IP_P3IP 8 /* PCI Express Port 3 */ +#define D28IP_P2IP 4 /* PCI Express Port 2 */ +#define D28IP_P1IP 0 /* PCI Express Port 1 */ +#define D27IP 0x3110 /* 32bit */ +#define D27IP_ZIP 0 /* HD Audio Pin */ +#define D26IP 0x3114 /* 32bit */ +#define D26IP_E2P 0 /* EHCI #2 Pin */ +#define D25IP 0x3118 /* 32bit */ +#define D25IP_LIP 0 /* GbE LAN Pin */ +#define D22IP 0x3124 /* 32bit */ +#define D22IP_KTIP 12 /* KT Pin */ +#define D22IP_IDERIP 8 /* IDE-R Pin */ +#define D22IP_MEI2IP 4 /* MEI #2 Pin */ +#define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCIIP 0 + +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ +#define D23IR 0x3158 /* 16bit */ +#define D22IR 0x315c /* 16bit */ +#define D21IR 0x3164 /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define D19IR 0x3168 /* 16bit */ + +#define OIC 0x31ff /* 8bit */ + +#define DIR_ROUTE(x, a, b, c, d) \ + (RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR))) + +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ +#define PCH_DISABLE_GBE (1 << 5) +#define FD 0x3418 /* 32bit */ +#define DISPBDF 0x3424 /* 16bit */ +#define FD2 0x3428 /* 32bit */ +#define CG 0x341c /* 32bit */ + +/* Function Disable 1 RCBA 0x3418 */ +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) +#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_SATA1 (1 << 2) +#define PCH_DISABLE_SMBUS (1 << 3) +#define PCH_DISABLE_HD_AUDIO (1 << 4) +#define PCH_DISABLE_EHCI2 (1 << 13) +#define PCH_DISABLE_LPC (1 << 14) +#define PCH_DISABLE_EHCI1 (1 << 15) +#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) +#define PCH_DISABLE_THERMAL (1 << 24) +#define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) + +/* Function Disable 2 RCBA 0x3428 */ +#define PCH_DISABLE_KT (1 << 4) +#define PCH_DISABLE_IDER (1 << 3) +#define PCH_DISABLE_MEI2 (1 << 2) +#define PCH_DISABLE_MEI1 (1 << 1) +#define PCH_ENABLE_DBDF (1 << 0) + +/* Function Disable (FD) register values. + * Setting a bit disables the corresponding + * feature. + * Not all features might be disabled on + * all chipsets. Esp. ICH-7U is picky. + */ +#define FD_PCIE6 (1 << 21) +#define FD_PCIE5 (1 << 20) +#define FD_PCIE4 (1 << 19) +#define FD_PCIE3 (1 << 18) +#define FD_PCIE2 (1 << 17) +#define FD_PCIE1 (1 << 16) +#define FD_EHCI (1 << 15) +#define FD_LPCB (1 << 14) + +/* UHCI must be disabled from 4 downwards. + * If UHCI controllers get disabled, EHCI + * must know about it, too! */ +#define FD_UHCI4 (1 << 11) +#define FD_UHCI34 ((1 << 10) | FD_UHCI4) +#define FD_UHCI234 ((1 << 9) | FD_UHCI3) +#define FD_UHCI1234 ((1 << 8) | FD_UHCI2) + +#define FD_INTLAN (1 << 7) +#define FD_ACMOD (1 << 6) +#define FD_ACAUD (1 << 5) +#define FD_HDAUD (1 << 4) +#define FD_SMBUS (1 << 3) +#define FD_SATA (1 << 2) +#define FD_PATA (1 << 1) + +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 186115472f..44d2f3d911 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -2,7 +2,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/common/acpi_pirq_gen.h> -#include <southbridge/intel/common/rcba_pirq.h> +#include <southbridge/intel/common/rcba.h> #define MAX_SLOT 31 #define MIN_SLOT 19 diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h deleted file mode 100644 index cf76fb32f5..0000000000 --- a/src/southbridge/intel/common/rcba_pirq.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H -#define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H - -/* - * The DnnIR registers use common RCBA offsets across these chipsets: - * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint - * - * However not all registers are in use on all of these. - */ - -#define D31IR 0x3140 /* 16bit */ -#define D30IR 0x3142 /* 16bit */ -#define D29IR 0x3144 /* 16bit */ -#define D28IR 0x3146 /* 16bit */ -#define D27IR 0x3148 /* 16bit */ -#define D26IR 0x314c /* 16bit */ -#define D25IR 0x3150 /* 16bit */ -#define D23IR 0x3158 /* 16bit */ -#define D22IR 0x315c /* 16bit */ -#define D21IR 0x3164 /* 16bit */ -#define D20IR 0x3160 /* 16bit */ -#define D19IR 0x3168 /* 16bit */ - -#define DEFAULT_RCBA 0xfed1c000 - -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) - -#endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */ diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index d9f635a925..964c3b286c 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <delay.h> #include <device/azalia_device.h> +#include <southbridge/intel/common/rcba.h> #include "pch.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index bc50f94d6b..559ad0603f 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -35,6 +35,7 @@ #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <southbridge/intel/common/rcba.h> #define NMI_OFF 0 diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 70dbcbf54f..e260650e8f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -30,6 +30,7 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <southbridge/intel/common/rcba.h> #ifdef __SMM__ #include <arch/io.h> diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 1898ae3dba..d3c5a66db6 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -47,12 +47,6 @@ #define DEFAULT_PMBASE 0x0500 #ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 #if defined (__SMM__) && !defined(__ASSEMBLER__) @@ -241,75 +235,6 @@ void southbridge_configure_default_intmap(void); /* Root Complex Register Block */ #define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ -#define RPFN 0x0404 /* 32bit */ - -/* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) -/* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) -/* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) -/* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) - -#define TRSR 0x1e00 /* 8bit */ -#define TRCR 0x1e10 /* 64bit */ -#define TWDR 0x1e18 /* 64bit */ - -#define IOTR0 0x1e80 /* 64bit */ -#define IOTR1 0x1e88 /* 64bit */ -#define IOTR2 0x1e90 /* 64bit */ -#define IOTR3 0x1e98 /* 64bit */ - -#define TCTL 0x3000 /* 8bit */ - #define NOINT 0 #define INTA 1 #define INTB 2 @@ -338,86 +263,9 @@ void southbridge_configure_default_intmap(void); #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) -#define D31IP 0x3100 /* 32bit */ -#define D31IP_TTIP 24 /* Thermal Throttle Pin */ -#define D31IP_SIP2 20 /* SATA Pin 2 */ -#define D31IP_UNKIP 16 -#define D31IP_SMIP 12 /* SMBUS Pin */ -#define D31IP_SIP 8 /* SATA Pin */ -#define D30IP 0x3104 /* 32bit */ -#define D30IP_PIP 0 /* PCI Bridge Pin */ -#define D29IP 0x3108 /* 32bit */ -#define D29IP_E1P 0 /* EHCI #1 Pin */ -#define D28IP 0x310c /* 32bit */ -#define D28IP_P8IP 28 /* PCI Express Port 8 */ -#define D28IP_P7IP 24 /* PCI Express Port 7 */ -#define D28IP_P6IP 20 /* PCI Express Port 6 */ -#define D28IP_P5IP 16 /* PCI Express Port 5 */ -#define D28IP_P4IP 12 /* PCI Express Port 4 */ -#define D28IP_P3IP 8 /* PCI Express Port 3 */ -#define D28IP_P2IP 4 /* PCI Express Port 2 */ -#define D28IP_P1IP 0 /* PCI Express Port 1 */ -#define D27IP 0x3110 /* 32bit */ -#define D27IP_ZIP 0 /* HD Audio Pin */ -#define D26IP 0x3114 /* 32bit */ -#define D26IP_E2P 0 /* EHCI #2 Pin */ -#define D25IP 0x3118 /* 32bit */ -#define D25IP_LIP 0 /* GbE LAN Pin */ -#define D22IP 0x3124 /* 32bit */ -#define D22IP_KTIP 12 /* KT Pin */ -#define D22IP_IDERIP 8 /* IDE-R Pin */ -#define D22IP_MEI2IP 4 /* MEI #2 Pin */ -#define D22IP_MEI1IP 0 /* MEI #1 Pin */ -#define D20IP 0x3128 /* 32bit */ -#define D20IP_XHCIIP 0 -#define D31IR 0x3140 /* 16bit */ -#define D30IR 0x3142 /* 16bit */ -#define D29IR 0x3144 /* 16bit */ -#define D28IR 0x3146 /* 16bit */ -#define D27IR 0x3148 /* 16bit */ -#define D26IR 0x314c /* 16bit */ -#define D25IR 0x3150 /* 16bit */ -#define D22IR 0x315c /* 16bit */ -#define D20IR 0x3160 /* 16bit */ -#define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) - -#define RC 0x3400 /* 32bit */ -#define HPTC 0x3404 /* 32bit */ -#define GCS 0x3410 /* 32bit */ -#define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) -#define FD 0x3418 /* 32bit */ -#define DISPBDF 0x3424 /* 16bit */ -#define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ - -/* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) -#define PCH_DISABLE_P2P (1 << 1) -#define PCH_DISABLE_SATA1 (1 << 2) -#define PCH_DISABLE_SMBUS (1 << 3) -#define PCH_DISABLE_HD_AUDIO (1 << 4) -#define PCH_DISABLE_EHCI2 (1 << 13) -#define PCH_DISABLE_LPC (1 << 14) -#define PCH_DISABLE_EHCI1 (1 << 15) -#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) -#define PCH_DISABLE_THERMAL (1 << 24) -#define PCH_DISABLE_SATA2 (1 << 25) -#define PCH_DISABLE_XHCI (1 << 27) - -/* Function Disable 2 RCBA 0x3428 */ -#define PCH_DISABLE_KT (1 << 4) -#define PCH_DISABLE_IDER (1 << 3) -#define PCH_DISABLE_MEI2 (1 << 2) -#define PCH_DISABLE_MEI1 (1 << 1) -#define PCH_ENABLE_DBDF (1 << 0) - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 08cf3b7fe1..29c46e8379 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -24,6 +24,7 @@ #include <halt.h> #include <pc80/mc146818rtc.h> #include "pch.h" +#include <southbridge/intel/common/rcba.h> #include "nvs.h" diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 5d3c90f840..315367df50 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -22,6 +22,7 @@ #include "pch.h" #include <device/pci_ehci.h> #include <arch/io.h> +#include <southbridge/intel/common/rcba.h> static void usb_ehci_init(struct device *dev) { |