4 files changed, 107 insertions, 0 deletions
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h
index de1209a84c..d90a85f3f3 100644
--- a/src/arch/mips/include/arch/cache.h
+++ b/src/arch/mips/include/arch/cache.h
@@ -41,4 +41,11 @@ void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation);
 /* Invalidate all caches: instruction, data, L2 data */
 void cache_invalidate_all(uintptr_t start, size_t size);
 
+/* TODO: Global cache API. Implement properly once we finally have a MIPS board
+   again where we can figure out what exactly these should be doing. */
+static inline void cache_sync_instructions(void) {}
+static inline void dcache_clean_all(void) {}
+static inline void dcache_invalidate_all(void) {}
+static inline void dcache_clean_invalidate_all(void) {}
+
 #endif /* __MIPS_ARCH_CACHE_H */
diff --git a/src/arch/power8/include/arch/cache.h b/src/arch/power8/include/arch/cache.h
new file mode 100644
index 0000000000..9b91ac2164
--- /dev/null
+++ b/src/arch/power8/include/arch/cache.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef ARCH_CACHE_H
+#define ARCH_CACHE_H
+
+/* TODO: implement these API stubs once caching is available on Power 8 */
+static inline void cache_sync_instructions(void) {}
+static inline void dcache_clean_all(void) {}
+static inline void dcache_invalidate_all(void) {}
+static inline void dcache_clean_invalidate_all(void) {}
+
+#endif /* ARCH_CACHE_H */
diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h
new file mode 100644
index 0000000000..ba7c33da47
--- /dev/null
+++ b/src/arch/riscv/include/arch/cache.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef ARCH_CACHE_H
+#define ARCH_CACHE_H
+
+/* TODO: implement these API stubs once caching is available on RISC-V */
+static inline void cache_sync_instructions(void) {}
+static inline void dcache_clean_all(void) {}
+static inline void dcache_invalidate_all(void) {}
+static inline void dcache_clean_invalidate_all(void) {}
+
+#endif /* ARCH_CACHE_H */
diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h
index 687d3bf9d3..9f7cda2643 100644
--- a/src/arch/x86/include/arch/cache.h
+++ b/src/arch/x86/include/arch/cache.h
@@ -31,6 +31,9 @@
 #ifndef ARCH_CACHE_H
 #define ARCH_CACHE_H
 
+#include <arch/early_variables.h>
+#include <cpu/x86/cache.h>
+
 /*
  * For the purposes of the currently executing CPU loading code that will be
  * run there aren't any cache coherency operations required. This just provides
@@ -38,4 +41,21 @@
  */
 static inline void cache_sync_instructions(void) {}
 
+/* Executing WBINVD when running out of CAR would not be good, prevent that. */
+static inline void dcache_clean_invalidate_all(void)
+{
+	if (!car_active())
+		wbinvd();
+}
+static inline void dcache_clean_all(void)
+{
+	/* x86 doesn't have a "clean without invalidate", fall back to both. */
+	dcache_clean_invalidate_all();
+}
+static inline void dcache_invalidate_all(void)
+{
+	if (!car_active())
+		invd();
+}
+
 #endif /* ARCH_CACHE_H */