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-rw-r--r--src/cpu/intel/model_2065x/finalize.c3
-rw-r--r--src/cpu/intel/model_2065x/model_2065x.h1
-rw-r--r--src/northbridge/intel/nehalem/finalize.c12
3 files changed, 0 insertions, 16 deletions
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index 50e00bf74a..5e7b3d847c 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -54,7 +54,4 @@ void intel_model_2065x_finalize_smm(void)
/* Lock TM interupts - route thermal events to all processors */
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
-
- /* Lock memory configuration to protect SMM */
- msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
}
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 8bb3b877e8..f87ba77460 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -39,7 +39,6 @@
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
-#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
index f90f93769f..7313840606 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -23,18 +23,6 @@
void intel_nehalem_finalize_smm(void)
{
- pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
- pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
- pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
- pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
- pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
- pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
- pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
- pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
- pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
- pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
- pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
-
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */