3 files changed, 155 insertions, 1 deletions
diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl
index 6b37e48dd1..98208e0989 100644
--- a/src/mainboard/google/parrot/acpi/mainboard.asl
+++ b/src/mainboard/google/parrot/acpi/mainboard.asl
@@ -101,3 +101,6 @@ Scope (\_SB) {
 	}
 
 }
+
+/* USB port entries */
+#include "acpi/usb.asl"
diff --git a/src/mainboard/google/parrot/acpi/usb.asl b/src/mainboard/google/parrot/acpi/usb.asl
new file mode 100644
index 0000000000..fc992db30b
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/usb.asl
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.EHC1.HUB7.PRT1)
+{
+	// Hub Port 1
+	Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+	{
+		0xFF,	// Connectable
+		0xFF,	// OEM Connector
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Not Visible
+	Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+	{
+		Return (GPLD (Zero))
+	}
+
+	Device (USB2)
+	{
+		Name (_ADR, 2)
+
+		// Left USB Port
+		Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+		{
+			0xFF,	// Connectable
+			Zero,	// USB Port
+			Zero,	// Reserved
+			Zero	// Reserved
+		})
+
+		// Visible
+		Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+		{
+			Return (GPLD (One))
+		}
+
+	}
+
+	Device (USB3)
+	{
+		Name (_ADR, 3)
+
+		// Bottom Right USB Port
+		Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+		{
+			0xFF,	// Connectable
+			Zero,	// USB Port
+			Zero,	// Reserved
+			Zero	// Reserved
+		})
+
+		// Visible
+		Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+		{
+			Return (GPLD (One))
+		}
+	}
+
+	Device (USB4)
+	{
+		Name (_ADR, 4)
+
+		// Top Right USB Port
+		Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+		{
+			0xFF,	// Connectable
+			Zero,	// USB Port
+			Zero,	// Reserved
+			Zero	// Reserved
+		})
+
+		// Visible
+		Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+		{
+			Return (GPLD (One))
+		}
+	}
+
+}
+
+Scope (_SB.PCI0.EHC2.HUB7.PRT1)
+{
+	// Hub Port 2
+	Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+	{
+		0xFF,	// Connectable
+		0xFF,	// OEM Connector
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Not Visible
+	Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+	{
+		Return (GPLD (Zero))
+	}
+
+	Device (USB1)
+	{
+		Name (_ADR, 1)
+
+		// Bluetooth
+		Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+		{
+			0xFF,	// Connectable
+			0xFF,	// OEM Connector
+			Zero,	// Reserved
+			Zero	// Reserved
+		})
+
+		// Not Visible
+		Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+		{
+			Return (GPLD (Zero))
+		}
+	}
+
+	Device (USB3)
+	{
+		Name (_ADR, 3)
+
+		// Webcam
+		Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+		{
+			0xFF,	// Connectable
+			0xFF,	// OEM Connector
+			Zero,	// Reserved
+			Zero	// Reserved
+		})
+
+		// Not Visible
+		Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+		{
+			Return (GPLD (Zero))
+		}
+	}
+}
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 3e13a41c12..d179dea91a 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -27,7 +27,6 @@ DefinitionBlock(
 
 	// Some generic macros
 	#include "acpi/platform.asl"
-	#include "acpi/mainboard.asl"
 
 	// global NVS and variables
 	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
@@ -50,6 +49,8 @@ DefinitionBlock(
 		}
 	}
 
+	#include "acpi/mainboard.asl"
+
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */