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-rw-r--r--src/soc/intel/fsp_baytrail/spi.c72
1 files changed, 37 insertions, 35 deletions
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 1b85fc58ee..374e7f6a44 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2016 Siemens AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -158,64 +159,65 @@ enum {
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#define SPI_OFFSET_MASK 0x3ff
-static u8 readb_(const void *addr)
+static uint8_t readb_(const void *addr)
{
- u8 v = read8(addr);
- printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ uint8_t v = read8(addr);
+ if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+ printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n",
+ v, (((uint32_t) addr) & SPI_OFFSET_MASK));
+ }
return v;
}
-static u16 readw_(const void *addr)
+static uint16_t readw_(const void *addr)
{
- u16 v = read16(addr);
- printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ uint16_t v = read16(addr);
+ if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+ printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n",
+ v, (((uint32_t) addr) & SPI_OFFSET_MASK));
+ }
return v;
}
-static u32 readl_(const void *addr)
+static uint32_t readl_(const void *addr)
{
- u32 v = read32(addr);
- printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ uint32_t v = read32(addr);
+ if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+ printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n",
+ v, (((uint32_t) addr) & SPI_OFFSET_MASK));
+ }
return v;
}
-static void writeb_(u8 b, void *addr)
+static void writeb_(uint8_t b, void *addr)
{
write8(addr, b);
- printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+ printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n",
+ b, (((uint32_t) addr) & SPI_OFFSET_MASK));
+ }
}
-static void writew_(u16 b, void *addr)
+static void writew_(uint16_t b, void *addr)
{
write16(addr, b);
- printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+ printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n",
+ b, (((uint32_t) addr) & SPI_OFFSET_MASK));
+ }
}
-static void writel_(u32 b, void *addr)
+static void writel_(uint32_t b, void *addr)
{
write32(addr, b);
- printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+ printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n",
+ b, (((uint32_t) addr) & SPI_OFFSET_MASK));
+ }
}
-#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-
-#define readb_(a) read8(a)
-#define readw_(a) read16(a)
-#define readl_(a) read32(a)
-#define writeb_(val, addr) write8(addr, val)
-#define writew_(val, addr) write16(addr, val)
-#define writel_(val, addr) write32(addr, val)
-
-#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-
static void write_reg(const void *value, void *dest, uint32_t size)
{
const uint8_t *bvalue = value;
@@ -441,10 +443,10 @@ static int spi_setup_offset(spi_transaction *trans)
*
* Return the last read status value on success or -1 on failure.
*/
-static int ich_status_poll(u16 bitmask, int wait_til_set)
+static int ich_status_poll(uint16_t bitmask, int wait_til_set)
{
int timeout = 40000; /* This will result in 400 ms */
- u16 status = 0;
+ uint16_t status = 0;
while (timeout--) {
status = readw_(cntlr.status);