44 files changed, 25 insertions, 25 deletions
diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb
index 65f7ee4577..8dd067128f 100644
--- a/src/mainboard/amd/olivehillplus/devicetree.cb
+++ b/src/mainboard/amd/olivehillplus/devicetree.cb
@@ -41,7 +41,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 				device pci 8.0 on  end # Platform Security Processor
 			end	#chip northbridge/amd/pi/00730F01
 
-			chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus
+			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0
 				device pci 11.0 on  end # SATA
 				device pci 12.0 on  end # USB
@@ -60,7 +60,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 				device pci 14.3 on  end # LPC	0x439d
 				device pci 14.7 on  end # SD
 				device pci 16.0 on  end # USB
-			end	#chip southbridge/amd/pi/avalon
+			end	#chip southbridge/amd/pi/hudson
 
 			device pci 18.0 on  end
 			device pci 18.1 on  end
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
index 56381e18f3..68ed74e84a 100644
--- a/src/mainboard/amd/olivehillplus/dsdt.asl
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -37,13 +37,13 @@ DefinitionBlock (
 	#include "acpi/usb_oc.asl"
 
 	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/avalon/acpi/pcie.asl>
+	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
 
 	/* Describe the processor tree (\_PR) */
 	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/pi/avalon/acpi/sleepstates.asl>
+	#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
 
 	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
 	#include "acpi/sleep.asl"
@@ -68,16 +68,16 @@ DefinitionBlock (
 			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
 
 			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/avalon/acpi/fch.asl>
+			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
 		}
 
 		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/avalon/acpi/pci_int.asl>
+		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
 
 	} /* End \_SB scope */
 
 	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/avalon/acpi/smbus.asl>
+	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
 
 	/* Define the General Purpose Events for the platform */
 	#include "acpi/gpe.asl"
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index 80ba5b5af7..d49c998332 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -27,7 +27,7 @@
 #include <cpu/amd/amdfam15.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/avalon/hudson.h> /* pm_ioread() */
+#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */
 
 u8 picr_data[0x54] = {
 	0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 63044ed4d0..6b081c653e 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -34,7 +34,7 @@
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/avalon/hudson.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
 #include <cpu/amd/pi/s3_resume.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/southbridge/amd/pi/Kconfig b/src/southbridge/amd/pi/Kconfig
index a0438c87f3..2cbf748ff2 100644
--- a/src/southbridge/amd/pi/Kconfig
+++ b/src/southbridge/amd/pi/Kconfig
@@ -17,4 +17,4 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-source src/southbridge/amd/pi/avalon/Kconfig
+source src/southbridge/amd/pi/hudson/Kconfig
diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc
index b7bcc7a450..d8e492a36d 100644
--- a/src/southbridge/amd/pi/Makefile.inc
+++ b/src/southbridge/amd/pi/Makefile.inc
@@ -16,4 +16,4 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += avalon
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson
diff --git a/src/southbridge/amd/pi/avalon/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index c54138c890..a924ace727 100644
--- a/src/southbridge/amd/pi/avalon/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -27,7 +27,7 @@ if SOUTHBRIDGE_AMD_PI_AVALON
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/amd/pi/avalon/bootblock.c"
+	default "southbridge/amd/pi/hudson/bootblock.c"
 
 config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT
 	bool
@@ -172,7 +172,7 @@ config HUDSON_AHCI_ROM
 config AHCI_ROM_FILE
 	string "AHCI ROM path and filename"
 	depends on HUDSON_AHCI_ROM
-	default "src/southbridge/amd/pi/avalon/ahci.bin"
+	default "src/southbridge/amd/pi/hudson/ahci.bin"
 
 endif
 
@@ -186,11 +186,11 @@ config RAID_ROM_ID
 
 config RAID_ROM_FILE
 	string "RAID ROM path and filename"
-	default "src/southbridge/amd/pi/avalon/raid.bin"
+	default "src/southbridge/amd/pi/hudson/raid.bin"
 
 config RAID_MISC_ROM_FILE
 	string "RAID Misc ROM path and filename"
-	default "src/southbridge/amd/pi/avalon/misc.bin"
+	default "src/southbridge/amd/pi/hudson/misc.bin"
 
 config RAID_MISC_ROM_POSITION
 	hex "RAID Misc ROM Position"
diff --git a/src/southbridge/amd/pi/avalon/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 06e95a6737..e0b26f8aa6 100644
--- a/src/southbridge/amd/pi/avalon/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -28,7 +28,7 @@
 #
 #*****************************************************************************
 
-INCLUDES += -Isrc/southbridge/amd/pi/avalon
+INCLUDES += -Isrc/southbridge/amd/pi/hudson
 
 romstage-y += smbus.c smbus_spd.c
 ramstage-y += hudson.c
diff --git a/src/southbridge/amd/pi/avalon/acpi/audio.asl b/src/southbridge/amd/pi/hudson/acpi/audio.asl
index 2c25ab5bd0..2c25ab5bd0 100644
--- a/src/southbridge/amd/pi/avalon/acpi/audio.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/audio.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index f2764aaa08..f2764aaa08 100644
--- a/src/southbridge/amd/pi/avalon/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/lpc.asl b/src/southbridge/amd/pi/hudson/acpi/lpc.asl
index 3383ac8cdd..3383ac8cdd 100644
--- a/src/southbridge/amd/pi/avalon/acpi/lpc.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/lpc.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl
index 384ed6128e..384ed6128e 100644
--- a/src/southbridge/amd/pi/avalon/acpi/pci_int.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/pcie.asl b/src/southbridge/amd/pi/hudson/acpi/pcie.asl
index f130fb45d2..f130fb45d2 100644
--- a/src/southbridge/amd/pi/avalon/acpi/pcie.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/pcie.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/sleepstates.asl b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl
index f8d0bb0855..f8d0bb0855 100644
--- a/src/southbridge/amd/pi/avalon/acpi/sleepstates.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/smbus.asl b/src/southbridge/amd/pi/hudson/acpi/smbus.asl
index 11aff4a04d..11aff4a04d 100644
--- a/src/southbridge/amd/pi/avalon/acpi/smbus.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/smbus.asl
diff --git a/src/southbridge/amd/pi/avalon/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl
index 4ec338e88f..4ec338e88f 100644
--- a/src/southbridge/amd/pi/avalon/acpi/usb.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl
diff --git a/src/southbridge/amd/pi/avalon/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
index e6bd2da4f5..e6bd2da4f5 100644
--- a/src/southbridge/amd/pi/avalon/amd_pci_int_defs.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
diff --git a/src/southbridge/amd/pi/avalon/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index d0fe9c8094..d0fe9c8094 100644
--- a/src/southbridge/amd/pi/avalon/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
diff --git a/src/southbridge/amd/pi/avalon/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index 3cdba8b907..3cdba8b907 100644
--- a/src/southbridge/amd/pi/avalon/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
diff --git a/src/southbridge/amd/pi/avalon/chip.h b/src/southbridge/amd/pi/hudson/chip.h
index 40b2480df2..001ba7b934 100644
--- a/src/southbridge/amd/pi/avalon/chip.h
+++ b/src/southbridge/amd/pi/hudson/chip.h
@@ -17,10 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef AVALON_CHIP_H
-#define AVALON_CHIP_H
+#ifndef HUDSON_CHIP_H
+#define HUDSON_CHIP_H
 
-struct southbridge_amd_pi_avalon_config
+struct southbridge_amd_pi_hudson_config
 {
 	#if 1
 	u32 ide0_enable : 1;
@@ -32,4 +32,4 @@ struct southbridge_amd_pi_avalon_config
 	#endif
 };
 
-#endif /* AVALON_CHIP_H */
+#endif /* HUDSON_CHIP_H */
diff --git a/src/southbridge/amd/pi/avalon/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 9500d0ec27..9500d0ec27 100644
--- a/src/southbridge/amd/pi/avalon/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
diff --git a/src/southbridge/amd/pi/avalon/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
index 258267ed04..258267ed04 100644
--- a/src/southbridge/amd/pi/avalon/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
diff --git a/src/southbridge/amd/pi/avalon/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index f86016ab8b..f86016ab8b 100644
--- a/src/southbridge/amd/pi/avalon/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
diff --git a/src/southbridge/amd/pi/avalon/hda.c b/src/southbridge/amd/pi/hudson/hda.c
index 2e648b7c6f..2e648b7c6f 100644
--- a/src/southbridge/amd/pi/avalon/hda.c
+++ b/src/southbridge/amd/pi/hudson/hda.c
diff --git a/src/southbridge/amd/pi/avalon/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c
index 3c07ed26cf..e5382b410d 100644
--- a/src/southbridge/amd/pi/avalon/hudson.c
+++ b/src/southbridge/amd/pi/hudson/hudson.c
@@ -33,7 +33,7 @@
 
 /* Offsets from ACPI_MMIO_BASE
  * This is defined by AGESA, but we don't include AGESA headers to avoid
- * polluting the namesace.
+ * polluting the namespace.
  */
 #define PM_MMIO_BASE 0xfed80300
 
@@ -132,7 +132,7 @@ static void hudson_final(void *chip_info)
 {
 }
 
-struct chip_operations southbridge_amd_pi_avalon_ops = {
+struct chip_operations southbridge_amd_pi_hudson_ops = {
 	CHIP_NAME("ATI HUDSON")
 	.enable_dev = hudson_enable,
 	.init = hudson_init,
diff --git a/src/southbridge/amd/pi/avalon/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 90c3205ed1..90c3205ed1 100644
--- a/src/southbridge/amd/pi/avalon/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
diff --git a/src/southbridge/amd/pi/avalon/ide.c b/src/southbridge/amd/pi/hudson/ide.c
index cd80f99ff4..cd80f99ff4 100644
--- a/src/southbridge/amd/pi/avalon/ide.c
+++ b/src/southbridge/amd/pi/hudson/ide.c
diff --git a/src/southbridge/amd/pi/avalon/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index d15a6d12ed..d15a6d12ed 100644
--- a/src/southbridge/amd/pi/avalon/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
diff --git a/src/southbridge/amd/pi/avalon/pci.c b/src/southbridge/amd/pi/hudson/pci.c
index e8836e4c7d..e8836e4c7d 100644
--- a/src/southbridge/amd/pi/avalon/pci.c
+++ b/src/southbridge/amd/pi/hudson/pci.c
diff --git a/src/southbridge/amd/pi/avalon/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h
index d2549d47b3..d2549d47b3 100644
--- a/src/southbridge/amd/pi/avalon/pci_devs.h
+++ b/src/southbridge/amd/pi/hudson/pci_devs.h
diff --git a/src/southbridge/amd/pi/avalon/pcie.c b/src/southbridge/amd/pi/hudson/pcie.c
index ec686fc2cf..ec686fc2cf 100644
--- a/src/southbridge/amd/pi/avalon/pcie.c
+++ b/src/southbridge/amd/pi/hudson/pcie.c
diff --git a/src/southbridge/amd/pi/avalon/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index 79fd79e210..79fd79e210 100644
--- a/src/southbridge/amd/pi/avalon/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
diff --git a/src/southbridge/amd/pi/avalon/sata.c b/src/southbridge/amd/pi/hudson/sata.c
index c02a5b119c..c02a5b119c 100644
--- a/src/southbridge/amd/pi/avalon/sata.c
+++ b/src/southbridge/amd/pi/hudson/sata.c
diff --git a/src/southbridge/amd/pi/avalon/sd.c b/src/southbridge/amd/pi/hudson/sd.c
index 4367f7aa6a..03b097a0c5 100644
--- a/src/southbridge/amd/pi/avalon/sd.c
+++ b/src/southbridge/amd/pi/hudson/sd.c
@@ -31,8 +31,8 @@ static void sd_init(struct device *dev)
 
 	stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
 
-	struct southbridge_amd_pi_avalon_config *sd_chip =
-		(struct southbridge_amd_pi_avalon_config *)(dev->chip_info);
+	struct southbridge_amd_pi_hudson_config *sd_chip =
+		(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
 
 	if (sd_chip->sd_mode == 3) {	/* SD 3.0 mode */
 		pci_write_config32(dev, 0xA4, 0x31FEC8B2);
diff --git a/src/southbridge/amd/pi/avalon/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index d6ca215a6a..d6ca215a6a 100644
--- a/src/southbridge/amd/pi/avalon/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
diff --git a/src/southbridge/amd/pi/avalon/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c
index 519c85dc2b..519c85dc2b 100644
--- a/src/southbridge/amd/pi/avalon/smbus.c
+++ b/src/southbridge/amd/pi/hudson/smbus.c
diff --git a/src/southbridge/amd/pi/avalon/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h
index 53cc0e6c44..53cc0e6c44 100644
--- a/src/southbridge/amd/pi/avalon/smbus.h
+++ b/src/southbridge/amd/pi/hudson/smbus.h
diff --git a/src/southbridge/amd/pi/avalon/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c
index 9dfd0b5f97..9dfd0b5f97 100644
--- a/src/southbridge/amd/pi/avalon/smbus_spd.c
+++ b/src/southbridge/amd/pi/hudson/smbus_spd.c
diff --git a/src/southbridge/amd/pi/avalon/smi.c b/src/southbridge/amd/pi/hudson/smi.c
index 1d58afe3f8..1d58afe3f8 100644
--- a/src/southbridge/amd/pi/avalon/smi.c
+++ b/src/southbridge/amd/pi/hudson/smi.c
diff --git a/src/southbridge/amd/pi/avalon/smi.h b/src/southbridge/amd/pi/hudson/smi.h
index de987a9274..de987a9274 100644
--- a/src/southbridge/amd/pi/avalon/smi.h
+++ b/src/southbridge/amd/pi/hudson/smi.h
diff --git a/src/southbridge/amd/pi/avalon/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c
index 6076cd43b3..6076cd43b3 100644
--- a/src/southbridge/amd/pi/avalon/smi_util.c
+++ b/src/southbridge/amd/pi/hudson/smi_util.c
diff --git a/src/southbridge/amd/pi/avalon/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c
index e762d0bb96..e762d0bb96 100644
--- a/src/southbridge/amd/pi/avalon/smihandler.c
+++ b/src/southbridge/amd/pi/hudson/smihandler.c
diff --git a/src/southbridge/amd/pi/avalon/usb.c b/src/southbridge/amd/pi/hudson/usb.c
index 36eff6e820..36eff6e820 100644
--- a/src/southbridge/amd/pi/avalon/usb.c
+++ b/src/southbridge/amd/pi/hudson/usb.c
diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc
index 72c71d458a..a302e336c4 100644
--- a/src/vendorcode/amd/pi/00730F01/Makefile.inc
+++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc
@@ -47,7 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
 AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
 AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
 
-AGESA_INC += -I$(src)/southbridge/amd/pi/avalon
+AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include