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-rw-r--r--src/include/cpu/x86/smm.h1
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c2
-rw-r--r--src/southbridge/intel/lynxpoint/usb_xhci.c4
3 files changed, 4 insertions, 3 deletions
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 513b6df708..9db1461d9d 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -24,6 +24,7 @@
#define APM_CNT_ACPI_ENABLE 0xe1
#define APM_CNT_MBI_UPDATE 0xeb
#define APM_CNT_GNVS_UPDATE 0xea
+#define APM_CNT_ROUTE_ALL_XHCI 0xca
#define APM_CNT_FINALIZE 0xcb
#define APM_CNT_LEGACY 0xcc
#define APM_CNT_SMMINFO 0xec
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 8bbe3feaa4..be842c5720 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -330,7 +330,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
- case 0xca:
+ case APM_CNT_ROUTE_ALL_XHCI:
usb_xhci_route_all();
break;
case APM_CNT_ELOG_GSMI:
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 8684aa9b32..1cfec1b476 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/x86/smm.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include "chip.h"
@@ -356,7 +356,7 @@ static void usb_xhci_init(struct device *dev)
usb_xhci_reset_usb3(dev, 0);
} else if (config->xhci_default) {
/* Route all ports to XHCI */
- outb(0xca, 0xb2);
+ apm_control(APM_CNT_ROUTE_ALL_XHCI);
}
}