diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 7 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 3bdefc4d74..17f824c87d 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev) { u32 reg32; + /* Assign unique bus/dev/fn for I/O APIC */ + pci_write_config16(dev, LPC_IBDF, + PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); + /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); @@ -375,9 +379,15 @@ static void ppt_pm_init(struct device *dev) RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } -static void enable_hpet(void) +static void enable_hpet(struct device *const dev) { u32 reg32; + size_t i; + + /* Assign unique bus/dev/fn for each HPET */ + for (i = 0; i < 8; ++i) + pci_write_config16(dev, LPC_HnBDF(i), + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); @@ -531,7 +541,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); + enable_hpet(dev); /* Initialize Clock Gating */ enable_clock_gating(dev); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2c42a39725..ba4391d999 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -120,6 +120,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 +#define PCH_IOAPIC_PCI_BUS 250 +#define PCH_IOAPIC_PCI_SLOT 31 +#define PCH_HPET_PCI_BUS 250 +#define PCH_HPET_PCI_SLOT 15 /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) @@ -159,6 +163,9 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B +#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ +#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ + #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |