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-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c40
-rw-r--r--src/mainboard/amd/persimmon/BiosCallOuts.c79
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c31
-rw-r--r--src/vendorcode/amd/agesa/f14/gcccar.inc84
4 files changed, 117 insertions, 117 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 6f697cf3da..577da1ba0d 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -37,22 +37,22 @@
msr_t rdmsr_amd(u32 index)
{
- msr_t result;
- __asm__ __volatile__(
- "rdmsr"
- :"=a"(result.lo), "=d"(result.hi)
- :"c"(index), "D"(0x9c5a203a)
- );
- return result;
+ msr_t result;
+ __asm__ __volatile__(
+ "rdmsr"
+ :"=a"(result.lo), "=d"(result.hi)
+ :"c"(index), "D"(0x9c5a203a)
+ );
+ return result;
}
void wrmsr_amd(u32 index, msr_t msr)
{
- __asm__ __volatile__(
- "wrmsr"
- : /* No outputs */
- :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
- );
+ __asm__ __volatile__(
+ "wrmsr"
+ : /* No outputs */
+ :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
+ );
}
static void model_14_init(device_t dev)
@@ -123,18 +123,18 @@ static void model_14_init(device_t dev)
}
static struct device_operations cpu_dev_ops = {
- .init = model_14_init,
+ .init = model_14_init,
};
static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */
- { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */
- { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */
- { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */
- { 0, 0 },
+ { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */
+ { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */
+ { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */
+ { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */
+ { 0, 0 },
};
static const struct cpu_driver model_14 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
};
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index c8379ff16f..7323832eee 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS CalloutStatus;
UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+ /*
+ * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func);
+ */
+
CalloutStatus = AGESA_UNSUPPORTED;
for (i = 0; i < CallOutCount; i++) {
@@ -95,20 +99,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
- UINT32 AvailableHeapSize;
- UINT8 *BiosHeapBaseAddr;
- UINT32 CurrNodeOffset;
- UINT32 PrevNodeOffset;
- UINT32 FreedNodeOffset;
- UINT32 BestFitNodeOffset;
- UINT32 BestFitPrevNodeOffset;
- UINT32 NextFreeOffset;
- BIOS_BUFFER_NODE *CurrNodePtr;
- BIOS_BUFFER_NODE *FreedNodePtr;
- BIOS_BUFFER_NODE *BestFitNodePtr;
- BIOS_BUFFER_NODE *BestFitPrevNodePtr;
- BIOS_BUFFER_NODE *NextFreePtr;
- BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
AGESA_BUFFER_PARAMS *AllocParams;
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
@@ -149,8 +153,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
}
CurrNodeOffset = CurrNodePtr->NextNodeOffset;
/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
- to the end of the allocated nodes list.
+ to the end of the allocated nodes list.
*/
+
}
/* Find the node that best fits the requested buffer size */
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@@ -199,7 +204,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
}
/* If BestFitNode is the first buffer in the list, then update
- StartOfFreedNodes to reflect the new free node
+ StartOfFreedNodes to reflect the new free node
*/
if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
@@ -249,7 +254,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
PrevNodeOffset = AllocNodeOffset;
- while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
if (AllocNodePtr->NextNodeOffset == 0) {
return AGESA_BOUNDS_CHK;
}
@@ -283,10 +288,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* Clear the BufferSize and NextNodeOffset of the previous first node */
FreedNodePtr->BufferSize = 0;
FreedNodePtr->NextNodeOffset = 0;
+
} else {
/* Otherwise, add freed node to the start of the list
- Update NextNodeOffset and BufferSize to include the
- size of BIOS_BUFFER_NODE
+ Update NextNodeOffset and BufferSize to include the
+ size of BIOS_BUFFER_NODE
*/
AllocNodePtr->NextNodeOffset = FreedNodeOffset;
}
@@ -294,21 +300,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
} else {
/* Traverse list of freed nodes to find where the deallocated node
- should be place
+ should be place
*/
NextNodeOffset = FreedNodeOffset;
NextNodePtr = FreedNodePtr;
while (AllocNodeOffset > NextNodeOffset) {
PrevNodeOffset = NextNodeOffset;
if (NextNodePtr->NextNodeOffset == 0) {
- break;
+ break;
}
NextNodeOffset = NextNodePtr->NextNodeOffset;
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
}
/* If deallocated node is adjacent to the next node,
- concatenate both nodes
+ concatenate both nodes
*/
if (NextNodeOffset == EndNodeOffset) {
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
@@ -322,13 +328,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocNodePtr->NextNodeOffset = NextNodeOffset;
}
/* If deallocated node is adjacent to the previous node,
- concatenate both nodes
+ concatenate both nodes
*/
PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
if (AllocNodeOffset == EndNodeOffset) {
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
AllocNodePtr->BufferSize = 0;
AllocNodePtr->NextNodeOffset = 0;
} else {
@@ -398,17 +405,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
// 0xCF9 (Reset Port).
//
switch (ResetType) {
- case WARM_RESET_WHENEVER:
- case COLD_RESET_WHENEVER:
+ case WARM_RESET_WHENEVER:
+ case COLD_RESET_WHENEVER:
break;
- case WARM_RESET_IMMEDIATELY:
- case COLD_RESET_IMMEDIATELY:
- Value = 0x06;
- LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+ case WARM_RESET_IMMEDIATELY:
+ case COLD_RESET_IMMEDIATELY:
+ Value = 0x06;
+ LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
break;
- default:
+ default:
break;
}
@@ -555,13 +562,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
case 4:
switch (ResetInfo->ResetControl) {
- case AssertSlotReset:
+ case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
- case DeassertSlotReset:
+ case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
@@ -571,13 +578,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
break;
case 6:
switch (ResetInfo->ResetControl) {
- case AssertSlotReset:
+ case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
- case DeassertSlotReset:
+ case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
@@ -587,13 +594,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
break;
case 7:
switch (ResetInfo->ResetControl) {
- case AssertSlotReset:
+ case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
- case DeassertSlotReset:
+ case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
index c4c3892e5a..ae9f3c7fd8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
@@ -25,7 +25,7 @@
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@@ -33,10 +33,10 @@
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -47,7 +47,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
* ***************************************************************************
*
*/
@@ -66,47 +66,40 @@
*----------------------------------------------------------------------------------------
*/
-// typedef unsigned int uintptr_t;
+// typedef unsigned int uintptr_t;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
-
-VOID
-ExecuteFinalHltInstruction (
- IN UINT32 SharedCore,
- IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
+
VOID
SetIdtr (
IN IDT_BASE_LIMIT *IdtInfo,
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
);
-
+
VOID
GetCsSelector (
IN UINT16 *Selector,
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
);
-
+
VOID
NmiHandler (
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
);
-
+
VOID
ExecuteHltInstruction (
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
);
-
+
VOID
ExecuteWbinvdInstruction (
IN AMD_CONFIG_PARAMS *StdHeader
);
-
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 63f3ea9d12..874391982b 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@@ -9,10 +9,10 @@
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -23,9 +23,9 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*/
-
+
/******************************************************************************
* AMD Generic Encapsulated Software Architecture
*
@@ -144,28 +144,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
* CPU MACROS - PUBLIC
*
****************************************************************************/
-.macro _WRMSR
- .byte 0x0f, 0x30
+.macro _WRMSR
+ .byte 0x0f, 0x30
.endm
-.macro _RDMSR
- .byte 0x0F, 0x32
+.macro _RDMSR
+ .byte 0x0F, 0x32
.endm
.macro AMD_CPUID arg0
- .ifb \arg0
- mov $0x1, %eax
+ .ifb \arg0
+ mov $0x1, %eax
.byte 0x0F, 0x0A2 /* Execute instruction */
- bswap %eax
+ bswap %eax
xchg %ah, %al /* Ext model in al now */
rol $0x08, %eax /* Ext model in ah, model in al */
and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */
.else
- mov \arg0, %eax
- .byte 0x0F, 0x0A2
+ mov \arg0, %eax
+ .byte 0x0F, 0x0A2
.endif
.endm
-
+
/****************************************************************************
*
* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
@@ -180,12 +180,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK
- AMD_ENABLE_STACK_FAMILY_HOOK_F10
- AMD_ENABLE_STACK_FAMILY_HOOK_F12
- AMD_ENABLE_STACK_FAMILY_HOOK_F14
- AMD_ENABLE_STACK_FAMILY_HOOK_F15
+ AMD_ENABLE_STACK_FAMILY_HOOK_F10
+ AMD_ENABLE_STACK_FAMILY_HOOK_F12
+ AMD_ENABLE_STACK_FAMILY_HOOK_F14
+ AMD_ENABLE_STACK_FAMILY_HOOK_F15
.endm
-
+
/****************************************************************************
*
* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
@@ -206,7 +206,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
AMD_DISABLE_STACK_FAMILY_HOOK_F15
.endm
-
+
/****************************************************************************
*
* GET_NODE_ID_CORE_ID Macro - Stackless
@@ -238,9 +238,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
*/
cmp $-1, %si # Has family (node/core) already been discovered?
jnz node_core_exit # Br if yes
-
+
mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
-
+
mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
_RDMSR
bt $APIC_BSC, %eax # Is this the BSC?
@@ -249,7 +249,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
node_core_exit:
.endm
-
+
/****************************************************************************
## Family 10h MACROS
##***************************************************************************
@@ -277,7 +277,7 @@ node_core_exit:
# * MSRC001_102A[ClLinesToNbDis]=1
# * No INVD or WBINVD, no exceptions, page faults or interrupts
****************************************************************************/
-.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
LOCAL fam10_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
@@ -310,7 +310,7 @@ node_core_exit:
jc fam10_skipClearingBit4
btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
_WRMSR
-
+
fam10_skipClearingBit4:
mov %esi, %eax # load core#
or %al, %al # If (BSP)
@@ -333,7 +333,7 @@ fam10_skipClearingBit4:
fam10_enable_stack_hook_exit:
.endm
-
+
/****************************************************************************
*
* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
@@ -357,7 +357,7 @@ fam10_enable_stack_hook_exit:
* * MSRC001_102A[IcDisSpecTlbWr]=0
* * MSRC001_102A[ClLinesToNbDis]=0
*****************************************************************************/
-
+
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10
LOCAL fam10_disable_stack_hook_exit
@@ -413,7 +413,7 @@ fam10_enable_stack_hook_exit:
_WRMSR # Disable the event
fam10_disable_stack_hook_exit:
-.endm
+.endm
/****************************************************************************
*
@@ -575,7 +575,7 @@ node_core_f10_exit:
jc fam12_skipClearingBit4
btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
_WRMSR
-
+
fam12_skipClearingBit4:
mov $DE_CFG, %ecx # MSR:C001_1029
_RDMSR
@@ -879,7 +879,7 @@ node_core_f14_exit:
_RDMSR
btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
_WRMSR
-
+
fam15_skipClearingBit4:
mov $LS_CFG, %ecx # MSR:C001_1020
_RDMSR
@@ -959,7 +959,7 @@ fam15_enable_stack_hook_exit:
btr $DIS_HW_PF, %eax # Turn on hardware prefetches
#.endif # End workaround for erratum 498
0:
- _WRMSR
+ _WRMSR
#--------------------------------------------------------------------------
# Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
#--------------------------------------------------------------------------
@@ -1121,7 +1121,7 @@ node_core_f15_shared:
#.break .if (ch == bl) # Does 2nd match MyCore#?
cmp %bl, %ch
je 9f
- jmp 2f
+ jmp 2f
#.else # No 2nd core
4:
#.break .if (ch == bl) # Does 1st match MyCore#?
@@ -1226,7 +1226,7 @@ node_core_f15_exit:
* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
*****************************************************************************/
-.macro AMD_ENABLE_STACK
+.macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors
LOCAL SetupStack
@@ -1294,7 +1294,7 @@ SetupStack:
#.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
# Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
# Clear all variable and Fixed MTRRs for non-shared cores
- jnc 0f
+ jnc 0f
mov $AMD_MTRR_VARIABLE_BASE0, %ecx
xor %eax, %eax
xor %edx, %edx
@@ -1330,20 +1330,20 @@ SetupStack:
_WRMSR
#.endif # End Is_Primary
#.endif # End Stack_ReEntry
- 0:
+ 0:
# Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor %eax, %eax
xor %edx, %edx
mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
#.while (cl != 1Ah)
jmp 1f
- 2:
+ 2:
_WRMSR
inc %cl
#.endw
- 1:
+ 1:
cmp $0x1A, %cl
- jne 2b
+ jne 2b
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
@@ -1414,7 +1414,7 @@ SetupStack:
mov %eax, %ebp
#.endif
0:
-
+
# Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
mov %bh, %cl # ShiftCount = ((slot# ...
@@ -1570,7 +1570,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is
* Destroyed:
* eax, ecx, edx, esp
*****************************************************************************/
-.macro AMD_DISABLE_STACK
+.macro AMD_DISABLE_STACK
mov %ebx, %esp # Save return address
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 14:31:23 +0000