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-rw-r--r--src/mainboard/amd/mahogany/romstage.c2
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c2
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c2
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c2
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c2
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c2
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c2
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/romstage.c2
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c2
-rw-r--r--src/southbridge/amd/sb700/sb700_enable_usbdebug.c30
10 files changed, 33 insertions, 15 deletions
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 1321a67bd7..16ea5f204f 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 6f47f66283..ad0d741762 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 3e190fec9c..536fe54c12 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index ac34a2d502..dac230734b 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 770cee1cbe..3df523cec6 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 13664418ab..55e1b62492 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 64b560d683..9569556228 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index e53ddf4251..96a4595cb6 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index b966c465e8..f96797d8c0 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
#if CONFIG_USBDEBUG
- sb700_enable_usbdebug(0);
+ sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
index 0f40d862a7..02d3900047 100644
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,22 +26,39 @@
#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */
#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */
-/* Required for successful build, but currently empty. */
+#define EHCI_EOR (EHCI_BAR + 0x20)
+#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80)
+
void set_debug_port(unsigned int port)
{
- /* TODO: Allow changing the physical USB port used as Debug Port. */
+ u32 reg32;
+
+ /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
+ reg32 = read32(DEBUGPORT_MISC_CONTROL);
+ reg32 &= ~(0xf << 28);
+ reg32 |= (port << 28);
+ reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
+ write32(DEBUGPORT_MISC_CONTROL, reg32);
}
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
static void sb700_enable_usbdebug(unsigned int port)
{
- device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
-
- /* Select the requested physical USB port (1-15) as the Debug Port. */
- set_debug_port(port);
+ device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+ /*
+ * Select the requested physical USB port (1-15) as the Debug Port.
+ * Must be called after the EHCI BAR has been set up (see above).
+ */
+ set_debug_port(port);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 17:00:12 +0000