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-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h1
-rw-r--r--src/soc/intel/xeon_sp/cpx/soc_util.c22
-rw-r--r--src/soc/intel/xeon_sp/nb_acpi.c44
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/soc_util.h1
-rw-r--r--src/soc/intel/xeon_sp/skx/soc_util.c28
5 files changed, 53 insertions, 43 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
index f0c257508a..5f4a6f9e2f 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
@@ -26,5 +26,6 @@ int get_threads_per_package(void);
const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void);
+int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index bc4a1e15b1..de6d8525c2 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -319,3 +319,25 @@ void set_bios_init_completion(void)
/* And finally, take care of the SBSP */
set_bios_init_completion_for_package(sbsp_socket_id);
}
+/*
+ * EX: CPX-SP
+ * Ports Stack Stack(HOB) IioConfigIou
+ * ==========================================
+ * 0 CSTACK stack 0 IOU0
+ * 1A..1D PSTACKZ stack 1 IOU1
+ * 2A..2D PSTACK1 stack 2 IOU2
+ * 3A..3D PSTACK2 stack 4 IOU3
+ */
+int soc_get_stack_for_port(int port)
+{
+ if (port == PORT_0)
+ return CSTACK;
+ else if (port >= PORT_1A && port <= PORT_1D)
+ return PSTACK0;
+ else if (port >= PORT_2A && port <= PORT_2D)
+ return PSTACK1;
+ else if (port >= PORT_3A && port <= PORT_3D)
+ return PSTACK2;
+ else
+ return -1;
+}
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index 5955fa0e31..f6bf6edf90 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -143,48 +143,6 @@ static unsigned long acpi_fill_slit(unsigned long current)
}
/*
- * EX: CPX-SP
- * Ports Stack Stack(HOB) IioConfigIou
- * ==========================================
- * 0 CSTACK stack 0 IOU0
- * 1A..1D PSTACKZ stack 1 IOU1
- * 2A..2D PSTACK1 stack 2 IOU2
- * 3A..3D PSTACK2 stack 4 IOU3
- */
-static int get_stack_for_port(int port)
-{
-#if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
- if (port == PORT_0)
- return CSTACK;
- else if (port >= PORT_1A && port <= PORT_1D)
- return PSTACK0;
- else if (port >= PORT_2A && port <= PORT_2D)
- return PSTACK1;
- else if (port >= PORT_3A && port <= PORT_3D)
- return PSTACK2;
- else
- return -1;
-#endif /* SOC_INTEL_COOPERLAKE_SP */
-
-#if (CONFIG(SOC_INTEL_SKYLAKE_SP))
- if (port == PORT_0)
- return CSTACK;
- else if (port >= PORT_1A && port <= PORT_1D)
- return PSTACK0;
- else if (port >= PORT_2A && port <= PORT_2D)
- return PSTACK1;
- else if (port >= PORT_3A && port <= PORT_3D)
- return PSTACK2;
- else if (port >= PORT_4A && port <= PORT_4D)
- return PSTACK3; // MCP0
- else if (port >= PORT_5A && port <= PORT_5D)
- return PSTACK4; // MCP1
- else
- return -1;
-#endif /* SOC_INTEL_SKYLAKE_SP */
-}
-
-/*
* This function adds PCIe bridge device entry in DMAR table. If it is called
* in the context of ATSR subtable, it adds ATSR subtable when it is first called.
*/
@@ -193,7 +151,7 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current,
bool is_atsr, bool *first)
{
- if (get_stack_for_port(port) != stack)
+ if (soc_get_stack_for_port(port) != stack)
return 0;
const uint32_t bus = iio_resource.StackRes[stack].BusBase;
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
index 25668301a4..cce542a1d5 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
@@ -27,5 +27,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void);
unsigned int soc_get_num_cpus(void);
+int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 7dd954fd66..3af6483dfe 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -394,4 +394,32 @@ void xeonsp_init_cpu_config(void)
}
}
+/*
+ * EX: SKX-SP
+ * Ports Stack Stack(HOB) IioConfigIou
+ * ==========================================
+ * 0 CSTACK stack 0 IOU0
+ * 1A..1D PSTACKZ stack 1 IOU1
+ * 2A..2D PSTACK1 stack 2 IOU2
+ * 3A..3D PSTACK2 stack 3 IOU3
+ * 5A..4D PSTACK3 stack 4 IOU4
+ * 5A..5D PSTACK4 stack 5 IOU5
+ */
+int soc_get_stack_for_port(int port)
+{
+ if (port == PORT_0)
+ return CSTACK;
+ else if (port >= PORT_1A && port <= PORT_1D)
+ return PSTACK0;
+ else if (port >= PORT_2A && port <= PORT_2D)
+ return PSTACK1;
+ else if (port >= PORT_3A && port <= PORT_3D)
+ return PSTACK2;
+ else if (port >= PORT_4A && port <= PORT_4D)
+ return PSTACK3; // MCP0
+ else if (port >= PORT_5A && port <= PORT_5D)
+ return PSTACK4; // MCP1
+ else
+ return -1;
+}
#endif