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-rw-r--r--src/mainboard/google/zoombini/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/zoombini/variants/meowth/devicetree.cb1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb1
-rw-r--r--src/soc/intel/cannonlake/chip.c2
-rw-r--r--src/soc/intel/cannonlake/chip.h7
6 files changed, 7 insertions, 6 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index 512354ed8f..6f70dfba2a 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index 4076ea6035..7d89b78e8b 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -29,7 +29,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 18aa65d890..d5d806c91e 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 8bcb850f15..4c62800483 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0c4232c277..924764a6c8 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -295,7 +295,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;
- params->SkipMpInit = config->FspSkipMpInit;
+ params->SkipMpInit = !config->use_fsp_mp_init;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 8fdb9646b3..d943f9c781 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -206,7 +206,12 @@ struct soc_intel_cannonlake_config {
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
} chipset_lockdown;
- uint8_t FspSkipMpInit;
+ /*
+ * Option for mainboard to skip coreboot MP initialization
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+ uint8_t use_fsp_mp_init;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */