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-rw-r--r--src/cpu/intel/model_f4x/microcode_MBDF410D.h2048
-rw-r--r--src/mainboard/asus/m2v-mx_se/Options.lb2
-rw-r--r--src/mainboard/dell/s1850/irq_tables.c96
-rw-r--r--src/mainboard/msi/ms9185/Options.lb2
-rw-r--r--src/mainboard/msi/ms9282/Options.lb4
-rw-r--r--src/mainboard/rca/rm4100/gpio.c286
-rw-r--r--src/mainboard/thomson/ip1000/gpio.c286
-rw-r--r--src/northbridge/intel/i82830/vga.c100
-rw-r--r--src/southbridge/intel/i82801ca/i82801ca_pci.c60
9 files changed, 1442 insertions, 1442 deletions
diff --git a/src/cpu/intel/model_f4x/microcode_MBDF410D.h b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
index 9266ce5c34..492262456c 100644
--- a/src/cpu/intel/model_f4x/microcode_MBDF410D.h
+++ b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
@@ -1,1024 +1,1024 @@
-0x00000001, /* Header Version */
-0x0000000d, /* Patch ID */
-0x11032004, /* DATE */
-0x00000f41, /* CPUID */
-0xa3430d74, /* Checksum */
-0x00000001, /* Loader Version */
-0x000000bd, /* Platform ID */
-0x00000fd0, /* Data size */
-0x00001000, /* Total size */
-0x00000000, /* reserved */
-0x00000000, /* reserved */
-0x00000000, /* reserved */
-0x23869663,
-0x00e8d132,
-0xc1efa329,
-0x20662968,
-0xb833cad6,
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+0xa814ec47,
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+0x2dfc2f4d,
+0xfa2ae308,
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+0x2acc1b4b,
+0x4f049f6f,
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+0x2db8f7b4,
+0xd61041a2,
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+0xb6ed3676,
+0x02aef566,
+0x2b6d41c8,
+0xaba9296e,
+0xf7b032cd,
+0xc290e538,
+0x584ad0f9,
+0x95289bc7,
+0x49b428b8,
+0x84bb41d4,
+0xdf0fcf91,
+0x9bd712a9,
+0xc6f730e1,
+0xe28b78d4,
+0x45b0480d,
+0x29d344bf,
+0xcd0101bb,
+0x18561b59,
+0xcfa84f65,
+0x76e798eb,
+0xac73f8af,
+0x71fe2488,
+0x207dd75d,
+0x198130e5,
+0x3604d44d,
+0xd895dc9b,
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+0x4fed2e51,
+0xf434e20a,
+0x7c3204e8,
+0x4d653a59,
+0x6652a556,
+0x8713f1e2,
+0xa69dea42,
+0x2fd0ee37,
+0xe7617993,
+0xc0791c80,
+0x57e14435,
+0x87fcad6e,
+0x96505f56,
+0x838e7a38,
+0x78b228ab,
+0x84411d16,
+0x0b4e1d87,
+0x21f17d96,
+0x72021b3c,
+0xe69f4784,
+0x324fb9b4,
+0x041c7459,
+0x500ffe39,
+0x6e561c0f,
+0xadaf6fd7,
+0x0c91509f,
+0x8be04594,
+0x6a5ead5a,
+0x313c9f9d,
+0xe4754919,
+0x63d7cebc,
+0x02d0ad32,
+0x2dc3cdb7,
+0xd9b2e421,
+0xa1ad018c,
+0xd954f545,
+0x9f3871b2,
+0xf8a9a4a9,
+0x4cdc558d,
+0x300c9685,
+0x639f4b78,
+0x2181680d,
+0xb96442d6,
+0x7821a1a2,
+0x174a9e5b,
+0x79320590,
+0xf580c60c,
+0xba8539ce,
+0x59905669,
+0xc6f39c94,
+0xb57cc9bf,
+0xc2f7ad76,
+0x8d9ebc2d,
+0x6c33e47f,
+0x29294c84,
+0x49a2bef6,
+0x8aa6f79b,
+0x809f0eb5,
+0x3691aa7f,
+0xcf4b0e8f,
+0xec44f802,
+0x16bf83a7,
+0x82c00d36,
+0xa99071b1,
+0xe3815c76,
+0xc0835331,
+0xc794c55f,
+0x041b44af,
+0x2fa75171,
+0x985bd852,
+0xc4391e66,
+0x7bf08eaf,
+0x2b826882,
+0xfb8834dc,
+0x9128681e,
+0x6a2cb9ef,
+0x6d1d20f9,
+0x9f90ee4d,
+0xc48c3ee3,
+0xdd063585,
+0x82454044,
+0xf7077f1a,
+0x47e6e556,
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+0x98f67f71,
+0x9089e4ac,
+0xe7f09610,
+0xa9e3f93b,
+0x420c1550,
+0xc01f7710,
+0x0905da5e,
+0x02d71f99,
+0xbf36b473,
+0x50a96e32,
+0x2dedb8b9,
+0x9e3051a2,
+0x84c023c4,
+0xd43073b1,
+0x74f23fbb,
+0xd42a4487,
+0x266dfc42,
+0x6be0acdf,
+0xa986294c,
+0x3ee65aa8,
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+0xa6a64910,
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+0xf1a60b7b,
+0x4cc9ea04,
+0x3cc95270,
+0x054a8d2b,
+0xae7a4525,
+0x2e2abb62,
+0x24b9522b,
+0xb95a6668,
+0xad8c237d,
+0x1ea73bf8,
+0xff33f0d6,
+0x772a16a3,
+0xfefabdc4,
+0xb181234c,
+0xab59fb47,
+0x96f2c987,
+0xff0d4f54,
+0x6e938aba,
+0x727e6266,
+0xea0d851f,
+0x2ced3474,
+0x8c2e7718,
+0xa576c375,
+0xc97addeb,
+0x2f46a635,
+0xdb669986,
+0xa4333f93,
+0x7042c2c6,
+0x419fda5f,
+0x95b8aa3f,
+0x6ad05dc8,
+0x8b90655a,
+0xd8c77947,
+0x20508480,
+0xfa3cdf6b,
+0xdbb44af2,
+0x235941d0,
+0x3154c107,
+0x566bc32a,
+0x426fb2cd,
+0xd2010afa,
+0xe2775abe,
+0x6f543a20,
+0x2c626450,
+0x34f193f4,
+0x37ac5908,
+0x58a7eca6,
+0xc4859881,
+0x183393ff,
+0xab9abed9,
+0xde947d21,
+0xffec2b7d,
+0xb21b8788,
+0xb527117f,
+0x199dffe5,
+0xd7ebe4e6,
+0xc89a72b0,
+0x91cc3042,
+0x91bd3463,
+0x736e6f4f,
+0x0cc208bc,
+0x029f21cb,
+0x3f204418,
+0x050db787,
+0x71b56562,
+0xaf07f08f,
+0xaca4701f,
+0x88d4f2f8,
+0xf98fe016,
+0xb47672c6,
+0xed601c94,
+0x285db8b8,
+0x28a81c19,
+0x9e2763ce,
+0xe39741c0,
+0xcd9fce6d,
+0xe9917796,
+0xfdd3ebaf,
+0x99dcb253,
+0xe9aa0db4,
+0x3a65c0b0,
+0xb39c61fb,
+0x1f413c5e,
+0x60576c8c,
+0x48d6df34,
+0x0cbca786,
+0x4caff4b7,
+0x8473e181,
+0x36eed747,
+0x82f486af,
+0x79f02eed,
+0xab6886ed,
+0x06aef911,
+0xad42a654,
+0x5471c813,
+0xc8bbe710,
+0xfc65fd97,
+0x60f467af,
+0xf56b71d8,
+0xc1d6f193,
+0x3a1c42bf,
+0x46ce3b78,
+0x39472626,
+0x04dc137e,
+0xb48dc9dd,
+0xdfd27741,
+0x4718e5a2,
+0x00ba4728,
+0x855b661f,
+0x6d98577f,
+0xc3b48131,
+0x2b0384c1,
+0x8af572fe,
+0x760aa4e3,
+0x2f5b53fb,
+0xb9234297,
+0x401b47f5,
+0x44237cc0,
+0x2f7205f4,
+0x19b63c6e,
+0x7c375e6b,
+0x152c42d8,
+0x603731c7,
+0xc67601fb,
+0xa5d4826c,
+0x9068966f,
+0x864fe2f9,
+0xb37311d9,
+0xe6e4a34a,
+0xd46ee161,
+0xecd76c4a,
+0x90d0328a,
+0x4865b540,
+0xd2e13982,
+0x7e3925f4,
+0xc850a518,
+0x63bffcce,
+0x7cdb918f,
+0xcd8786d3,
+0xcf83df01,
+0x27122e50,
+0x0f014b76,
+0xde1485d7,
+0xa6ff496f,
+0xed0812f7,
+0x34efe965,
+0x12a63465,
+0xb83d9f77,
+0x040efa2e,
+0x4ac576d1,
+0x185430dd,
+0xb4271745,
+0x9bb58be2,
+0x7f55d4bb,
+0xca7dae0b,
+0x0bfe5147,
+0x4a9ade45,
+0x20bdc545,
+0xdf66689d,
+0x22e29493,
+0x31763c1f,
+0x2d021cd2,
+0x06286428,
+0xc7bba5d4,
+0x6bc42a0e,
+0x1c987082,
+0xd6c6c2f9,
+0x2c1ecdd0,
+0x84946249,
+0x42c1c41b,
+0x6d949e60,
+0x9dbb1571,
+0xf6b1df68,
+0x0705ae1a,
+0xa1ec5add,
+0x7e94d7c8,
+0x7d4d451d,
+0xd53c13d4,
+0x0204877b,
+0x0f0e44e0,
+0xdf25570f,
+0xd2a9adaf,
+0x556aeacf,
+0x2f985a30,
+0x706c42c6,
+0x2d5a76a5,
+0xdc428213,
+0xdf2864a2,
+0x0f6788a9,
+0xc764d3a6,
+0x9211d0ca,
+0x59e3f5cc,
+0xd31fd5b6,
+0xfa8b535b,
+0x2cac74bb,
+0xc43f36b2,
+0xf83b5bac,
+0x96c255bf,
+0x45915993,
+0x657d751a,
+0x9b86b994,
+0xddab62fd,
+0x1b6ac108,
+0x559073c9,
+0xe60a0bda,
+0xd65df6de,
+0x41f7e5d4,
+0x825a5701,
+0x377307b6,
+0x08176ce6,
+0x7a8a2c4a,
+0xd7ecb869,
+0x02710179,
+0x75e7517c,
+0xdfaf2c82,
+0x67590275,
+0x6ad621af,
+0xaedaa35c,
+0xfa8fbee3,
+0x9e5dda5f,
+0x09f571fa,
+0xe358dbfe,
+0x1b3300f1,
+0x05567c6b,
+0x5a9d335f,
+0x215114f8,
+0xd5744f0a,
+0x78ecc142,
+0x9b5f60b8,
+0x30f8fed2,
+0x5c013696,
+0x675c84de,
+0xdb50bbcc,
+0x7c504a4e,
+0x3ffc5fda,
+0x24b2c30a,
+0xac00d64a,
+0x97832b52,
+0xb34d9975,
+0x93c6cb4e,
+0x471bfcae,
+0xaabbb6d8,
+0x0bc6a5e5,
+0x6875c630,
+0xf4cce30c,
+0xdab0d64b,
+0x29aba8b9,
+0xe34b3cde,
+0x8654e470,
+0x2c5041f7,
+0xdcf5eff9,
+0x26a88f84,
+0x9d374761,
+0xefa60ac4,
+0xdf0d0fd3,
+0x72e37e59,
+0xa76d26e1,
+0x3ffe2408,
+0x13ecf42d,
+0x46de7cba,
+0x43330219,
+0xc2536a31,
+0xa69c4729,
+0x114990f8,
+0x3f08ed00,
+0xeaa05cae,
+0x08f06e57,
+0x30f4a62f,
+0x963a7557,
+0x631fb75f,
+0x1344a74b,
+0x1e80cef5,
+0x8a4f86dd,
+0x0f7f1c62,
+0xfe9f5809,
+0x710d86de,
+0x8939283d,
+0x19403076,
+0x26ce286b,
+0x6baaf798,
+0xbc1d2808,
+0xea980728,
+0x72288979,
+0x7c92be68,
+0x0a7af91b,
+0x7bb8059b,
+0xe7eca99c,
+0xd3a8819f,
+0xb9182916,
+0x0c48ba1e,
+0xb6aaf63b,
+0x10a740a6,
+0x0aa2e4e7,
+0x0bf27e94,
+0x6d266f86,
diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb
index 93c1bd32e6..5d74fbce22 100644
--- a/src/mainboard/asus/m2v-mx_se/Options.lb
+++ b/src/mainboard/asus/m2v-mx_se/Options.lb
@@ -94,7 +94,7 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_USE_PRINTK_IN_CAR
default ROM_SIZE = 512 * 1024
default FALLBACK_SIZE = 256 * 1024
diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c
index d0e7be1cd9..dc5514bbac 100644
--- a/src/mainboard/dell/s1850/irq_tables.c
+++ b/src/mainboard/dell/s1850/irq_tables.c
@@ -1,48 +1,48 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*17, /* there can be total 17 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x24d0, /* Device */
- 0, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
- {0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
- {0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
- {0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
- {0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
- {0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
- {0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr);
-}
-
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*17, /* there can be total 17 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x24d0, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+ {0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+ {0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
+ {0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+ {0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
+ {0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
+ {0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
+
diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb
index efd5dc95bc..5c3073e2d2 100644
--- a/src/mainboard/msi/ms9185/Options.lb
+++ b/src/mainboard/msi/ms9185/Options.lb
@@ -220,7 +220,7 @@ default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcc000
default DCACHE_RAM_SIZE=0x04000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
index a666a8c61e..1a686826cd 100644
--- a/src/mainboard/msi/ms9282/Options.lb
+++ b/src/mainboard/msi/ms9282/Options.lb
@@ -100,7 +100,7 @@ uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_USE_PRINTK_IN_CAR
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
@@ -265,7 +265,7 @@ default CONFIG_GDB_STUB=0
## The Serial Console
##
default CONFIG_USE_PRINTK_IN_CAR=1
-
+
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c
index 97231e52a0..d51bc90e78 100644
--- a/src/mainboard/rca/rm4100/gpio.c
+++ b/src/mainboard/rca/rm4100/gpio.c
@@ -1,143 +1,143 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define PME_DEV PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
-#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- device_t dev;
- uint16_t port;
- uint32_t set_gpio;
-
- /* Southbridge GPIOs. */
- /* Set the LPC device statically. */
- dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
-
- /* Set GPIO23 to high, this enables the LAN controller. */
- udelay(10);
- set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
- set_gpio |= 1 << 23;
- outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
- /* Super I/O GPIOs. */
- dev = PME_DEV;
- port = dev >> 8;
-
- /* Enter the configuration state. */
- outb(0x55, port);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
- pnp_set_enable(dev, 1);
-
- /* GP21 - LED_RED */
- outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
- /* GP30 - FAN2_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
- /* GP31 - FAN1_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
- /* GP32 - FAN2_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
- /* GP33 - FAN1_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
- /* GP34 - AUD_MUTE_OUT_R */
- outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
- /* GP36 - KBRST */
- outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
- /* GP37 - A20GATE */
- outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
- /* GP42 - GPIO_PME_OUT */
- outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
- /* GP50 - SER2_RI */
- outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
- /* GP51 - SER2_DCD */
- outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
- /* GP52 - SER2_RX */
- outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
- /* GP53 - SER2_TX */
- outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
- /* GP55 - SER2_RTS */
- outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
- /* GP56 - SER2_CTS */
- outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
- /* GP57 - SER2_DTR */
- outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
- /* GP60 - LED_GREEN */
- outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
- /* GP61 - LED_YELLOW */
- outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
- /* GP3 */
- outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
- /* GP4 */
- outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
- /* FAN1 */
- outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
- /* FAN2 */
- outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
- /* Fan Control */
- outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
- /* Fan1 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
- /* Fan2 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
- /* LED1 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
- /* LED2 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
- /* Keyboard Scan Code */
- outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
- /* Exit the configuration state. */
- outb(0xaa, port);
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define PME_DEV PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
+#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ device_t dev;
+ uint16_t port;
+ uint32_t set_gpio;
+
+ /* Southbridge GPIOs. */
+ /* Set the LPC device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+ pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+ /* Set GPIO23 to high, this enables the LAN controller. */
+ udelay(10);
+ set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
+ set_gpio |= 1 << 23;
+ outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+ /* Super I/O GPIOs. */
+ dev = PME_DEV;
+ port = dev >> 8;
+
+ /* Enter the configuration state. */
+ outb(0x55, port);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+ pnp_set_enable(dev, 1);
+
+ /* GP21 - LED_RED */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2c);
+
+ /* GP30 - FAN2_TACH */
+ outl(0x05, PME_IO_BASE_ADDR + 0x33);
+
+ /* GP31 - FAN1_TACH */
+ outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+ /* GP32 - FAN2_CTRL */
+ outl(0x04, PME_IO_BASE_ADDR + 0x35);
+
+ /* GP33 - FAN1_CTRL */
+ outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+ /* GP34 - AUD_MUTE_OUT_R */
+ outl(0x00, PME_IO_BASE_ADDR + 0x37);
+
+ /* GP36 - KBRST */
+ outl(0x00, PME_IO_BASE_ADDR + 0x39);
+
+ /* GP37 - A20GATE */
+ outl(0x00, PME_IO_BASE_ADDR + 0x3a);
+
+ /* GP42 - GPIO_PME_OUT */
+ outl(0x00, PME_IO_BASE_ADDR + 0x3d);
+
+ /* GP50 - SER2_RI */
+ outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+ /* GP51 - SER2_DCD */
+ outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+ /* GP52 - SER2_RX */
+ outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+ /* GP53 - SER2_TX */
+ outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+ /* GP55 - SER2_RTS */
+ outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+ /* GP56 - SER2_CTS */
+ outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+ /* GP57 - SER2_DTR */
+ outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+ /* GP60 - LED_GREEN */
+ outl(0x01, PME_IO_BASE_ADDR + 0x47);
+
+ /* GP61 - LED_YELLOW */
+ outl(0x01, PME_IO_BASE_ADDR + 0x48);
+
+ /* GP3 */
+ outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
+
+ /* GP4 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x4e);
+
+ /* FAN1 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+ /* FAN2 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+ /* Fan Control */
+ outl(0x50, PME_IO_BASE_ADDR + 0x58);
+
+ /* Fan1 Tachometer */
+ outl(0xff, PME_IO_BASE_ADDR + 0x59);
+
+ /* Fan2 Tachometer */
+ outl(0xff, PME_IO_BASE_ADDR + 0x5a);
+
+ /* LED1 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5d);
+
+ /* LED2 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5e);
+
+ /* Keyboard Scan Code */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+ /* Exit the configuration state. */
+ outb(0xaa, port);
+}
diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c
index 97231e52a0..d51bc90e78 100644
--- a/src/mainboard/thomson/ip1000/gpio.c
+++ b/src/mainboard/thomson/ip1000/gpio.c
@@ -1,143 +1,143 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define PME_DEV PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
-#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- device_t dev;
- uint16_t port;
- uint32_t set_gpio;
-
- /* Southbridge GPIOs. */
- /* Set the LPC device statically. */
- dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
-
- /* Set GPIO23 to high, this enables the LAN controller. */
- udelay(10);
- set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
- set_gpio |= 1 << 23;
- outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
- /* Super I/O GPIOs. */
- dev = PME_DEV;
- port = dev >> 8;
-
- /* Enter the configuration state. */
- outb(0x55, port);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
- pnp_set_enable(dev, 1);
-
- /* GP21 - LED_RED */
- outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
- /* GP30 - FAN2_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
- /* GP31 - FAN1_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
- /* GP32 - FAN2_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
- /* GP33 - FAN1_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
- /* GP34 - AUD_MUTE_OUT_R */
- outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
- /* GP36 - KBRST */
- outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
- /* GP37 - A20GATE */
- outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
- /* GP42 - GPIO_PME_OUT */
- outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
- /* GP50 - SER2_RI */
- outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
- /* GP51 - SER2_DCD */
- outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
- /* GP52 - SER2_RX */
- outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
- /* GP53 - SER2_TX */
- outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
- /* GP55 - SER2_RTS */
- outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
- /* GP56 - SER2_CTS */
- outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
- /* GP57 - SER2_DTR */
- outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
- /* GP60 - LED_GREEN */
- outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
- /* GP61 - LED_YELLOW */
- outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
- /* GP3 */
- outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
- /* GP4 */
- outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
- /* FAN1 */
- outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
- /* FAN2 */
- outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
- /* Fan Control */
- outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
- /* Fan1 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
- /* Fan2 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
- /* LED1 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
- /* LED2 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
- /* Keyboard Scan Code */
- outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
- /* Exit the configuration state. */
- outb(0xaa, port);
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define PME_DEV PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
+#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ device_t dev;
+ uint16_t port;
+ uint32_t set_gpio;
+
+ /* Southbridge GPIOs. */
+ /* Set the LPC device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+ pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+ /* Set GPIO23 to high, this enables the LAN controller. */
+ udelay(10);
+ set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
+ set_gpio |= 1 << 23;
+ outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+ /* Super I/O GPIOs. */
+ dev = PME_DEV;
+ port = dev >> 8;
+
+ /* Enter the configuration state. */
+ outb(0x55, port);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+ pnp_set_enable(dev, 1);
+
+ /* GP21 - LED_RED */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2c);
+
+ /* GP30 - FAN2_TACH */
+ outl(0x05, PME_IO_BASE_ADDR + 0x33);
+
+ /* GP31 - FAN1_TACH */
+ outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+ /* GP32 - FAN2_CTRL */
+ outl(0x04, PME_IO_BASE_ADDR + 0x35);
+
+ /* GP33 - FAN1_CTRL */
+ outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+ /* GP34 - AUD_MUTE_OUT_R */
+ outl(0x00, PME_IO_BASE_ADDR + 0x37);
+
+ /* GP36 - KBRST */
+ outl(0x00, PME_IO_BASE_ADDR + 0x39);
+
+ /* GP37 - A20GATE */
+ outl(0x00, PME_IO_BASE_ADDR + 0x3a);
+
+ /* GP42 - GPIO_PME_OUT */
+ outl(0x00, PME_IO_BASE_ADDR + 0x3d);
+
+ /* GP50 - SER2_RI */
+ outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+ /* GP51 - SER2_DCD */
+ outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+ /* GP52 - SER2_RX */
+ outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+ /* GP53 - SER2_TX */
+ outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+ /* GP55 - SER2_RTS */
+ outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+ /* GP56 - SER2_CTS */
+ outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+ /* GP57 - SER2_DTR */
+ outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+ /* GP60 - LED_GREEN */
+ outl(0x01, PME_IO_BASE_ADDR + 0x47);
+
+ /* GP61 - LED_YELLOW */
+ outl(0x01, PME_IO_BASE_ADDR + 0x48);
+
+ /* GP3 */
+ outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
+
+ /* GP4 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x4e);
+
+ /* FAN1 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+ /* FAN2 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+ /* Fan Control */
+ outl(0x50, PME_IO_BASE_ADDR + 0x58);
+
+ /* Fan1 Tachometer */
+ outl(0xff, PME_IO_BASE_ADDR + 0x59);
+
+ /* Fan2 Tachometer */
+ outl(0xff, PME_IO_BASE_ADDR + 0x5a);
+
+ /* LED1 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5d);
+
+ /* LED2 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5e);
+
+ /* Keyboard Scan Code */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+ /* Exit the configuration state. */
+ outb(0xaa, port);
+}
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
index 7a6d1f7a6b..e9cfdac0c6 100644
--- a/src/northbridge/intel/i82830/vga.c
+++ b/src/northbridge/intel/i82830/vga.c
@@ -1,50 +1,50 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-static void vga_init(device_t dev) {
-
- printk_info("Starting Graphics Initialization\n");
- pci_dev_init(dev);
- printk_info("Graphics Initialization Complete\n");
- /* Future TV-OUT code will be called from here. */
-}
-
-static const struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .scan_bus = 0,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x3577,
-};
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Joseph Smith <joe@settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void vga_init(device_t dev) {
+
+ printk_info("Starting Graphics Initialization\n");
+ pci_dev_init(dev);
+ printk_info("Graphics Initialization Complete\n");
+ /* Future TV-OUT code will be called from here. */
+}
+
+static const struct device_operations vga_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vga_init,
+ .scan_bus = 0,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+ .ops = &vga_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x3577,
+};
diff --git a/src/southbridge/intel/i82801ca/i82801ca_pci.c b/src/southbridge/intel/i82801ca/i82801ca_pci.c
index 2508419d1b..5f7b89700e 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_pci.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_pci.c
@@ -1,30 +1,30 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ca.h"
-
-static void pci_init(struct device *dev)
-{
- // NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
- /* Enable pci error detecting */
- uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
- dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
- pci_write_config32(dev, PCI_COMMAND, dword);
-}
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pci_init,
- .scan_bus = pci_scan_bridge,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
-};
-
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ca.h"
+
+static void pci_init(struct device *dev)
+{
+ // NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
+ /* Enable pci error detecting */
+ uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
+ dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
+ pci_write_config32(dev, PCI_COMMAND, dword);
+}
+
+static struct device_operations pci_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pci_init,
+ .scan_bus = pci_scan_bridge,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+ .ops = &pci_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
+};
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 20:50:58 +0000