diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/graphics.c | 32 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/graphics.c | 33 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 42 | ||||
| -rw-r--r-- | src/soc/intel/icelake/graphics.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/graphics.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/skylake/graphics.c | 35 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/graphics.c | 30 |
7 files changed, 41 insertions, 191 deletions
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 2070baf14c..c8d282d837 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,42 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <stdint.h> -#include <acpi/acpi.h> -#include <bootmode.h> -#include <console/console.h> #include <fsp/util.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> #include <intelblocks/graphics.h> -#include <drivers/intel/gma/opregion.h> -#include <drivers/intel/gma/libgfxinit.h> #include <types.h> uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *const dev) -{ - intel_gma_init_igd_opregion(); - - if (CONFIG(RUN_FSP_GOP)) - return; - - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } -} diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 1db46254c5..cd5e773dbb 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -1,15 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> -#include <bootmode.h> -#include <console/console.h> #include <fsp/util.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/i915_reg.h> -#include <drivers/intel/gma/libgfxinit.h> -#include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -22,8 +16,6 @@ void graphics_soc_init(struct device *dev) { uint32_t ddi_buf_ctl; - intel_gma_init_igd_opregion(); - /* * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * This will allow the kernel to use 4-lane eDP links properly @@ -35,29 +27,4 @@ void graphics_soc_init(struct device *dev) DDI_BUF_IS_IDLE); graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - - /* IGD needs to Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. - */ - if (CONFIG(RUN_FSP_GOP)) { - /* nothing to do */ - } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ae45d67214..5110aad3d6 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> +#include <bootmode.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <soc/pci_devs.h> @@ -15,9 +18,7 @@ __weak void graphics_soc_init(struct device *dev) /* * User needs to implement SoC override in case wishes * to perform certain specific graphics initialization - * along with pci_dev_init(dev) */ - pci_dev_init(dev); } __weak const struct i915_gpu_controller_info * @@ -26,6 +27,41 @@ intel_igd_get_controller_info(const struct device *device) return NULL; } +static void gma_init(struct device *const dev) +{ + intel_gma_init_igd_opregion(); + + /* SoC specific configuration. */ + graphics_soc_init(dev); + + /* + * GFX PEIM module inside FSP binary is taking care of graphics + * initialization based on RUN_FSP_GOP Kconfig option and input + * VBT file. + * + * In case of non-FSP solution, SoC need to select another + * Kconfig to perform GFX initialization. + */ + if (CONFIG(RUN_FSP_GOP)) + return; + + /* IGD needs to Bus Master */ + u32 reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && display_init_required()) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } +} + static void gma_generate_ssdt(const struct device *device) { const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device); @@ -116,7 +152,7 @@ static const struct device_operations graphics_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = graphics_soc_init, + .init = gma_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = gma_generate_ssdt, diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 3118495498..c8d282d837 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <fsp/util.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -13,28 +8,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - intel_gma_init_igd_opregion(); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(RUN_FSP_GOP)) - return; - - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 3118495498..c8d282d837 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <fsp/util.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -13,28 +8,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - intel_gma_init_igd_opregion(); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(RUN_FSP_GOP)) - return; - - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index dab7e145d1..d88709777a 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -1,16 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> +#include <acpi/acpi.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <device/pci.h> -#include <device/pci_ops.h> +#include <device/mmio.h> #include <device/resource.h> #include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/i915_reg.h> -#include <drivers/intel/gma/libgfxinit.h> #include <intelblocks/graphics.h> -#include <drivers/intel/gma/opregion.h> #include <soc/ramstage.h> #include <types.h> @@ -83,8 +80,6 @@ void graphics_soc_init(struct device *dev) { u32 ddi_buf_ctl; - intel_gma_init_igd_opregion(); - graphics_setup_panel(dev); /* @@ -97,32 +92,6 @@ void graphics_soc_init(struct device *dev) ddi_buf_ctl |= DDI_A_4_LANES; graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - - /* IGD needs to Bus Master */ - u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. - */ - if (CONFIG(RUN_FSP_GOP)) { - /* nothing to do */ - } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } } const struct i915_gpu_controller_info * diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index ea90d44033..11aea72211 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -6,12 +6,7 @@ * Chapter number: 4 */ -#include <console/console.h> #include <fsp/util.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -19,28 +14,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - intel_gma_init_igd_opregion(); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(RUN_FSP_GOP)) - return; - - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} |