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-rw-r--r--src/soc/intel/cannonlake/acpi/gfx.asl20
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl3
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl
new file mode 100644
index 0000000000..d2678596c0
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/gfx.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000)
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index b52de65e36..8dbd850df6 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -31,6 +31,9 @@
#include "gpio.asl"
#endif
+/* GFX 00:02.0 */
+#include "gfx.asl"
+
/* LPC 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>