diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/rockchip/common/pwm.c (renamed from src/soc/rockchip/rk3288/pwm.c) | 20 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/clock.h | 2 |
4 files changed, 16 insertions, 12 deletions
diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/common/pwm.c index c609cb4afa..c294a0cdf2 100644 --- a/src/soc/rockchip/rk3288/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -32,12 +32,12 @@ struct pwm_ctl { u32 pwm_ctrl; }; -struct rk3288_pwm_regs { +struct rk_pwm_regs { struct pwm_ctl pwm[4]; u32 intsts; u32 int_en; }; -check_member(rk3288_pwm_regs, int_en, 0x44); +check_member(rk_pwm_regs, int_en, 0x44); #define RK_PWM_DISABLE (0 << 0) #define RK_PWM_ENABLE (1 << 0) @@ -62,23 +62,25 @@ check_member(rk3288_pwm_regs, int_en, 0x44); #define PWM_SEL_SCALE_CLK (1 << 9) #define PWM_SEL_SRC_CLK (0 << 9) -struct rk3288_pwm_regs *rk3288_pwm = (void *)RK_PWM0123_BASE; +struct rk_pwm_regs *rk_pwm = (void *)RK_PWM_BASE; void pwm_init(u32 id, u32 period_ns, u32 duty_ns) { unsigned long period, duty; +#if IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288) /*use rk pwm*/ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0)); +#endif - write32(&rk3288_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK | + write32(&rk_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE); - period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC; - duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC; + period = (PWM_CLOCK_HZ / 1000) * period_ns / USECS_PER_SEC; + duty = (PWM_CLOCK_HZ / 1000) * duty_ns / USECS_PER_SEC; - write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period); - write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty); - setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); + write32(&rk_pwm->pwm[id].pwm_period_hpr, period); + write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty); + setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); } diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index a57ead3da7..553bd00ba5 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -49,7 +49,7 @@ romstage-y += gpio.c romstage-y += ../common/spi.c romstage-y += sdram.c romstage-y += ../common/rk808.c -romstage-y += pwm.c +romstage-y += ../common/pwm.c romstage-y += tsadc.c ramstage-y += soc.c @@ -62,7 +62,7 @@ ramstage-y += ../common/spi.c ramstage-y += sdram.c ramstage-y += gpio.c ramstage-y += ../common/rk808.c -ramstage-y += pwm.c +ramstage-y += ../common/pwm.c ramstage-y += vop.c ramstage-y += edp.c ramstage-y += hdmi.c diff --git a/src/soc/rockchip/rk3288/include/soc/addressmap.h b/src/soc/rockchip/rk3288/include/soc/addressmap.h index fb07cafaed..ba59404f55 100644 --- a/src/soc/rockchip/rk3288/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3288/include/soc/addressmap.h @@ -52,7 +52,7 @@ #define I2C0_BASE 0xFF650000 #define I2C2_BASE 0xFF660000 #define DW_PWM0123_BASE 0xFF670000 -#define RK_PWM0123_BASE 0xFF680000 +#define RK_PWM_BASE 0xFF680000 #define UART2_BASE 0xFF690000 #define TIMER0_BASE 0xFF6B0000 diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 9592c985df..a629789762 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -39,6 +39,8 @@ enum apll_frequencies { #define PERI_HCLK_HZ (148500*KHz) #define PERI_PCLK_HZ (74250*KHz) +#define PWM_CLOCK_HZ PD_BUS_PCLK_HZ + void rkclk_init(void); void rkclk_configure_spi(unsigned int bus, unsigned int hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); |