11 files changed, 8 insertions, 44 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 789ea82db9..bc768527a8 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -20,7 +20,6 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include <stdlib.h>
 #include "i440bx.h"
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 6259608b48..61ddde98ca 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -20,7 +20,6 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include <stdlib.h>
 #include "i440lx.h"
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 86602eae34..fbb64f6088 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -21,7 +21,6 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include "i82810.h"
 
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index 27c48701ff..0bbf974108 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -20,7 +20,6 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include "lib/debug.c"
 #include "i82830.h"
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 7f7c997077..a0b3aab1c5 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -29,7 +29,6 @@
 /* ported from Via VT8263 Code*/
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include <cpu/x86/mtrr.h>
 #include "cn400.h"
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 72fb0c5a26..63dab5b3e0 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -21,7 +21,6 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include "cn700.h"
 
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index d68ad3b2c2..b562a867b9 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -20,7 +20,6 @@
 #include <types.h>
 #include <spd.h>
 #include <spd_ddr2.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include "cx700_registers.h"
 
diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index 394cfaeaf9..4daf2b785d 100644
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -18,7 +18,6 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 
 #if CONFIG_DEBUG_RAM_SETUP
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c
index 7f76a057ac..887c38e8de 100644
--- a/src/southbridge/amd/rs690/rs690_gfx.c
+++ b/src/southbridge/amd/rs690/rs690_gfx.c
@@ -34,6 +34,7 @@
 #define CLK_CNTL_INDEX	0x8
 #define CLK_CNTL_DATA	0xC
 
+#if 0
 static u32 clkind_read(device_t dev, u32 index)
 {
 	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
@@ -41,6 +42,7 @@ static u32 clkind_read(device_t dev, u32 index)
 	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
 	return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
 }
+#endif
 
 static void clkind_write(device_t dev, u32 index, u32 data)
 {
@@ -73,8 +75,6 @@ static void rs690_gfx_read_resources(device_t dev)
 static void internal_gfx_pci_dev_init(struct device *dev)
 {
 	u16 deviceid, vendorid;
-	struct southbridge_amd_rs690_config *cfg =
-	    (struct southbridge_amd_rs690_config *)dev->chip_info;
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
 	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
diff --git a/src/southbridge/amd/sb600/sb600_reset.c b/src/southbridge/amd/sb600/sb600_reset.c
index d6ea995a5c..af80576204 100644
--- a/src/southbridge/amd/sb600/sb600_reset.c
+++ b/src/southbridge/amd/sb600/sb600_reset.c
@@ -18,39 +18,10 @@
  */
 
 #include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <reset.h>
 
-#define PCI_DEV(BUS, DEV, FN) ( \
-	(((BUS) & 0xFFF) << 20) | \
-	(((DEV) & 0x1F) << 15) | \
-	(((FN)  & 0x7) << 12))
-
-typedef u32 device_t;
-
-static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
-{
-        unsigned addr;
-        addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outb(value, 0xCFC + (addr & 3));
-}
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
-{
-	unsigned addr;
-        addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(device_t dev, unsigned where)
-{
-	unsigned addr;
-        addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        return inl(0xCFC);
-}
-
-#include "../../../northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/reset_test.c"
 
 void hard_reset(void)
 {
diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c
index 5d2fde2a4c..8aca04d9a0 100644
--- a/src/southbridge/amd/sb700/sb700_early_setup.c
+++ b/src/southbridge/amd/sb700/sb700_early_setup.c
@@ -20,6 +20,7 @@
 #ifndef  _SB700_EARLY_SETUP_C_
 #define  _SB700_EARLY_SETUP_C_
 
+#include <reset.h>
 #include <arch/cpu.h>
 #include "sb700.h"
 #include "sb700_smbus.c"
@@ -214,7 +215,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	pmio_write(0x89, 0x10);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
 	set_bios_reset();
 
@@ -223,7 +224,7 @@ static void hard_reset(void)
 	outb(0x0e, 0x0cf9);
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */