diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/kahlee/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/devicetree.cb | 3 |
3 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index e212a57651..ad1a31220e 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select GFXUMA select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select STONEYRIDGE_UART @@ -51,7 +52,6 @@ config ONBOARD_VGA_IS_PRIMARY default y config VBOOT - select VBOOT_MOCK_SECDATA select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index a6161e4eba..caa24d5254 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -15,9 +15,13 @@ #include <bootblock_common.h> #include <ec.h> +#include <soc/hudson.h> void bootblock_mainboard_init(void) { /* Enable the EC as soon as we have visibility */ mainboard_ec_init(); + + /* Setup TPM decode before verstage */ + hudson_tpm_decode_spi(); } diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/devicetree.cb index fd43d1c903..0ed3336329 100644 --- a/src/mainboard/google/kahlee/devicetree.cb +++ b/src/mainboard/google/kahlee/devicetree.cb @@ -48,6 +48,9 @@ chip soc/amd/stoneyridge chip ec/google/chromeec device pnp 0c09.0 on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC 0x790e device pci 14.7 on end # SD device pci 18.0 on end |