diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/x86/Kconfig | 5 | ||||
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 4 |
2 files changed, 0 insertions, 9 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 4260278e02..07dfe45e64 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -70,11 +70,6 @@ config NO_FIXED_XIP_ROM_SIZE to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened. -config XIP_ROM_SIZE - hex - depends on !NO_FIXED_XIP_ROM_SIZE - default 0x10000 - config SETUP_XIP_CACHE bool depends on !NO_XIP_EARLY_STAGES diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 412330449f..9227710596 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -190,10 +190,6 @@ static inline unsigned int fls(unsigned int x) */ #define CACHE_TMP_RAMTOP (16<<20) -#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) -# error "CONFIG_XIP_ROM_SIZE is not a power of 2" -#endif - /* For ROM caching, generally, try to use the next power of 2. */ #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE) |