diff options
Diffstat (limited to 'src')
26 files changed, 61 insertions, 85 deletions
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c index 290fa864df..d2a3c58344 100644 --- a/src/cpu/amd/model_lx/vsmsetup.c +++ b/src/cpu/amd/model_lx/vsmsetup.c @@ -268,10 +268,7 @@ uint32_t VSA_msrRead(uint32_t msrAddr) void do_vsmbios(void) { - device_t dev; - unsigned long busdevfn; unsigned char *buf; - unsigned int size = SMM_SIZE * 1024; int i; printk(BIOS_ERR, "do_vsmbios\n"); diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index 6e43bf834f..09c9400e44 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -489,7 +489,10 @@ static void ati_ragexl_init(device_t dev) int j; u16 type; u8 rev; - const char *chipname = NULL, *xtal; + const char *chipname = NULL; +#if CONFIG_CONSOLE_BTEXT + const char *xtal; +#endif int pll, mclk, xclk; #if CONFIG_CONSOLE_BTEXT==1 diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 4bd7a45844..05f436e65e 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -39,10 +39,6 @@ #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) -static void memreset_setup(void) -{ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -53,8 +49,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { device_t dev; - u8 reg; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); @@ -89,9 +83,6 @@ static const struct mem_controller ctrl = { void main(unsigned long bist) { - unsigned long x; - device_t dev; - /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 1e4ee4c7eb..be696d97d4 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -51,7 +51,6 @@ static void msr_init(void) msr.hi = 0x20000000; msr.lo = 0xfff00; wrmsr(MSR_GLIU1 + 0x20, msr); - } static void mb_gpio_init(void) @@ -61,7 +60,6 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - extern void RestartCAR(); post_code(0x01); static const struct mem_controller memctrl [] = { diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 9f52466b6a..6aa3f0e404 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -50,8 +50,6 @@ static void *smp_write_config_table(void *v) static const char productid[12] = "TREX "; struct mp_config_table *mc; - unsigned char bus_num; - int i; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -78,11 +76,13 @@ static void *smp_write_config_table(void *v) /*Bus: Bus ID Type*/ /* define bus and isa numbers */ -/* for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { +#if 0 + unsigned char bus_num; + for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num); } - */ +#endif smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 7, "PCI "); diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 5de74a6cff..8f428e918f 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -57,7 +57,7 @@ uint64_t uma_memory_base, uma_memory_size; * RRG4.2.3.1 GPM pins as Input * RRG4.2.3.2 GPM pins as Output ********************************************************/ -static void enable_onboard_nic() +static void enable_onboard_nic(void) { u8 byte; @@ -94,7 +94,7 @@ static void enable_onboard_nic() * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to * get the cable type, 40 pin or 80 pin? ********************************************************/ -static void get_ide_dma66() +static void get_ide_dma66(void) { u8 byte; struct device *sm_dev; @@ -120,7 +120,7 @@ static void get_ide_dma66() /* * set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 1ba4440324..c4a9cc98e5 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -145,8 +145,6 @@ void cache_as_ram_main(void) {.channel0 = {0x50}}, }; - extern void RestartCAR(); - post_code(0x01); SystemPreInit(); diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 977196beb5..11deef2ad4 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -54,7 +54,7 @@ uint64_t uma_memory_base, uma_memory_size; * Both of their pin PERSTn pins are connected to GPIO 5 of the * SB600 southbridge. ****************************************************/ -static void enable_onboard_nic() +static void enable_onboard_nic(void) { u8 byte; @@ -80,7 +80,7 @@ static void enable_onboard_nic() /* set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index bb37481d10..be02ab3d3b 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1692,7 +1692,7 @@ void tuning(sMainData *pDat) * @param[out] result BOOL = true if check is ok, false if it failed * --------------------------------------------------------------------------------------- */ -BOOL isSanityCheckOk() +BOOL isSanityCheckOk(void) { uint64 qValue; diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 3f9e89d63c..190529ce04 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -123,9 +123,9 @@ struct msr_defaults { }; /* note that dev is NOT used -- yet */ -static void irq_init_steering(struct device *dev, uint16_t irq_map) { +static void irq_init_steering(struct device *dev, u16 irq_map) { /* Set up IRQ steering */ - uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; + u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); @@ -298,17 +298,17 @@ static void northbridge_init(device_t dev) /* this is a test -- we are not sure it will work -- but it ought to */ static void set_resources(struct device *dev) { +#if 0 struct resource *resource, *last; - unsigned link; - uint8_t line; -#if 0 last = &dev->resource[dev->resources]; for(resource = &dev->resource[0]; resource < last; resource++) { pci_set_resource(dev, resource); } #endif + unsigned link; + for(link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; @@ -327,7 +327,7 @@ static void set_resources(struct device *dev) } /* zero the irq settings */ - line = pci_read_config8(dev, PCI_INTERRUPT_PIN); + u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } @@ -383,10 +383,10 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new) } #if 0 -static uint32_t find_pci_tolm(struct bus *bus) +static u32 find_pci_tolm(struct bus *bus) { struct resource *min; - uint32_t tolm; + u32 tolm; min = 0; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); tolm = 0xffffffffUL; @@ -402,7 +402,7 @@ static void pci_domain_set_resources(device_t dev) { #if 0 device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm; pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 7d33e44236..5023edb546 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -60,7 +60,10 @@ static void northbridge_init(device_t dev) } } -static void nullfunc(){} +static void nullfunc(void) +{ + /* Nothing to do */ +} static struct device_operations northbridge_operations = { .read_resources = nullfunc, @@ -104,7 +107,7 @@ static const struct pci_driver agp_driver __pci_driver = { static void vga_init(device_t dev) { -// unsigned long fb; + //unsigned long fb; //msr_t clocks1,clocks2,instructions,setup; printk(BIOS_DEBUG, "VGA random fixup ...\n"); diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 7ec3c86aef..3a29d29aca 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -26,7 +26,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr); void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr); void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr); -CB_STATUS VerifyChc(); +CB_STATUS VerifyChc(void); /*=================================================================== Function : DRAMRegInitValue() diff --git a/src/northbridge/via/vx800/dram_init.c b/src/northbridge/via/vx800/dram_init.c index d059b519ef..b6c8cf2ab0 100644 --- a/src/northbridge/via/vx800/dram_init.c +++ b/src/northbridge/via/vx800/dram_init.c @@ -17,12 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -CB_STATUS DDR2_DRAM_INIT() +CB_STATUS DDR2_DRAM_INIT(void) { - CB_STATUS Status; u8 i; u32 RamSize; - BOOLEAN bTest; DRAM_SYS_ATTR DramAttr; PRINT_DEBUG_MEM("DRAM_INIT \r"); @@ -76,7 +74,7 @@ CB_STATUS DDR2_DRAM_INIT() PRINT_DEBUG_MEM_HEX32(RamSize); PRINT_DEBUG_MEM("\r"); DumpRegisters(0, 3); - //bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE); + //BOOLEAN bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE); /* the memory can not correct work, this is because the user set the incorrect memory parameter from setup interface.so we must set the boot mode to recovery mode, let the system to reset and use the spd value to initialize the memory */ diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index 51b98934e5..27f73f0f4d 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -253,9 +253,9 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr); void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr); /*set UMA*/ -void SetUMARam(); +void SetUMARam(void); CB_STATUS InstallMemory(DRAM_SYS_ATTR * DramAttr, u32 RamSize); -CB_STATUS DDR2_DRAM_INIT(); +CB_STATUS DDR2_DRAM_INIT(void); #endif diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 627fb28552..da8aae13c8 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -407,9 +407,6 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) u8 Data, CL, RDRPH; u8 CpuFreq, DramFreq; u8 ProgData[PT894_RDRDY_TBL_Width]; - u8 DelayMode; - u8 DrdyMode; - u8 Index; /* this function has 3 switchs, correspond to 3 level of Drdy setting. @@ -483,16 +480,19 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) Data = pci_read_config8(MEMCTRL, 0x90); DramFreq = Data & 0x07; + u8 DelayMode; DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) DelayMode &= 0x01; //In 364, there is no 128 bit if (DelayMode == 1) { // DelayMode 1 + u8 Index; for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) ProgData[Index] = PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq] [Index]; } else { // DelayMode 0 + u8 Index; for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) ProgData[Index] = PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq] diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index b81b90de79..47a99c3cc1 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -120,7 +120,7 @@ static const u8 CL_DDR2[7] = { 0, 0, 20, 30, 40, 50, 60 }; void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) { u8 AllDimmSupportedCL, Tmp; - u8 CLMask, tmpMask, IndexDelta; + u8 CLMask, tmpMask; u8 SckId, BitId, TmpId; u16 CycTime, TmpCycTime; diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c index 4daf2b785d..ce9b7d4fab 100644 --- a/src/northbridge/via/vx800/raminit.c +++ b/src/northbridge/via/vx800/raminit.c @@ -55,9 +55,8 @@ * Support one dimm with up to 2 ranks */ -static void ddr2_ram_setup() +static void ddr2_ram_setup(void) { - u8 Data; CB_STATUS Status; PRINT_DEBUG_MEM("In ddr2_ram_setup\r"); diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index 00e1e47fa3..df39ce5899 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -138,7 +138,6 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) u32 Size; BOOLEAN HasThreeBitBA; u8 Data; - u32 Address; HasThreeBitBA = FALSE; for (Slot = 0; Slot < 2; Slot++) { diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index 6988ffe4b0..71379e7ec3 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -333,6 +333,7 @@ void SetUMARam(void) ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03d5); +#if 0 u8 table3c43c5[0x70] = { 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -395,9 +396,9 @@ void SetUMARam(void) 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; -#if 0 -//for(i=0;i<0xc0;i++) - for (i = 0; i < 0x40; i++) // + + //for(i=0;i<0xc0;i++) + for (i = 0; i < 0x40; i++) { outb(table3c0space[i], 0x03c0 + i); } @@ -410,6 +411,7 @@ void SetUMARam(void) outb(i, 0x03d4); outb(table3d43d5[i], 0x03d5); } + outb(0x92, 0x03d4); outb(0x80, 0x03d5); @@ -419,12 +421,12 @@ void SetUMARam(void) outb(0xe8, 0x03d4); outb(0x40, 0x03d5); #endif -//3d4 3d freq -//IO Port / Index: 3X5.3D -//Scratch Pad Register 4 -// outb(0x39,0x03c4);// - //outb(1 << SLD0F3Val ,0x03c5); +// 3d4 3d freq +// IO Port / Index: 3X5.3D +// Scratch Pad Register 4 +// outb(0x39,0x03c4); +// outb(1 << SLD0F3Val ,0x03c5); // #endif diff --git a/src/northbridge/via/vx800/vgabios.c b/src/northbridge/via/vx800/vgabios.c index f8029ae157..9690170d1e 100644 --- a/src/northbridge/via/vx800/vgabios.c +++ b/src/northbridge/via/vx800/vgabios.c @@ -299,8 +299,6 @@ void do_vgabios(void) unsigned char *buf; unsigned int size = 64 * 1024; int i; - u16 tmp; - u8 tmp8; printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); @@ -646,15 +644,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, unsigned long *pecx, unsigned long *peax, unsigned long *pflags) { - unsigned long edi = *pedi; - unsigned long esi = *pesi; - unsigned long ebp = *pebp; - unsigned long esp = *pesp; - unsigned long ebx = *pebx; - unsigned long edx = *pedx; - unsigned long ecx = *pecx; unsigned long eax = *peax; - unsigned long flags = *pflags; unsigned short func = (unsigned short)eax; int retval = 0; unsigned short devid, vendorid, devfn; diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c index 583602c3dd..fbb3647578 100644 --- a/src/southbridge/amd/cs5535/cs5535_early_setup.c +++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c @@ -23,11 +23,11 @@ static void cs5535_setup_extmsr(void) /* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */ msr.hi = msr.lo = 0x00000000; - if (CS5535_GLINK_PORT_NUM <= 4) { - msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8); - } else { - msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8); - } +#if CS5535_GLINK_PORT_NUM <= 4 + msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8); +#else + msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8); +#endif wrmsr(0x5000201e, msr); } diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h index a470b3714c..6e50a8cc84 100644 --- a/src/southbridge/amd/cs5536/cs5536_smbus2.h +++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h @@ -239,9 +239,9 @@ static void _doread(unsigned smbus_io_base, unsigned char device, *data++ = val; if (count > 1) { - int ret = smbus_wait(smbus_io_base); + ret = smbus_wait(smbus_io_base); if (ret) - return ret; + return; } count--; diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index 0ad5c74ee0..3b24d62c25 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -66,8 +66,6 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { - unsigned char global_control_register; - unsigned char global_status_register; unsigned char byte; unsigned char stat; int i; diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c index 6d776d38bd..06d9f273c4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c @@ -388,7 +388,7 @@ static int mcp55_early_setup_x(void) int mcp55_num = 0; unsigned busnx; unsigned devnx; - int ht_c_index,j; + int ht_c_index; /* FIXME: multi pci segment handling */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c index 7c7ad6954c..8d80409719 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c +++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c @@ -51,8 +51,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base); - fadt->firmware_ctrl = facs; - fadt->dsdt = dsdt; + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; fadt->preferred_pm_profile = 1; //check fadt->sci_int = 9; /* disable system management mode by setting to 0 */ @@ -108,9 +108,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c index 2687972afa..92bd9d8391 100644 --- a/src/southbridge/via/vt8235/vt8235.c +++ b/src/southbridge/via/vt8235/vt8235.c @@ -41,7 +41,7 @@ void dump_south(device_t dev0) } } -void set_led() +void set_led(void) { // set power led to steady now that lxbios has virtually done its job device_t dev; |