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-rw-r--r--src/mainboard/pcengines/apu1/OemCustomize.c1
-rw-r--r--src/mainboard/pcengines/apu1/platform_cfg.h2
-rw-r--r--src/mainboard/pcengines/apu2/BiosCallOuts.c2
-rw-r--r--src/mainboard/pcengines/apu2/irq_tables.c1
-rw-r--r--src/mainboard/pcengines/apu2/mainboard.c1
-rw-r--r--src/mainboard/pcengines/apu2/mptable.c2
6 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index dcc81c9f8a..d6edf03e8b 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <PlatformMemoryConfiguration.h>
diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h
index 6087b1504a..ef6f5baeaa 100644
--- a/src/mainboard/pcengines/apu1/platform_cfg.h
+++ b/src/mainboard/pcengines/apu1/platform_cfg.h
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-
#ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_
@@ -112,7 +111,6 @@
*/
#define SATA_PORT_MULT_CAP_RESERVED 1
-
/**
* @def AZALIA_AUTO
* @brief Detect Azalia controller automatically.
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index a2065ae355..d17dc36617 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -27,7 +27,6 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }
-
/*
* Hardware Monitor Fan Control
* Hardware limitation:
@@ -58,7 +57,6 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
{
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
FchParams->Azalia.AzaliaEnable = AzDisable;
/* Fan Control */
diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c
index a16c247259..6c2b05c02b 100644
--- a/src/mainboard/pcengines/apu2/irq_tables.c
+++ b/src/mainboard/pcengines/apu2/irq_tables.c
@@ -25,7 +25,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
-
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index aa8c4bcf5e..939f7cbbb6 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -22,7 +22,6 @@
#define PM_RTC_CONTROL 0x56
#define PM_S_STATE_CONTROL 0xBA
-
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
* This table is responsible for physically routing the PIC and
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
index 8cfec5d63d..b52c8ccf49 100644
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -62,7 +62,6 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
@@ -85,7 +84,6 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
/* GPP0 */
PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
/* GPP1 */