summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rwxr-xr-xsrc/mainboard/supermicro/h8scm_fam10/Kconfig4
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/devicetree.cb4
-rw-r--r--src/southbridge/amd/Makefile.inc1
-rw-r--r--src/southbridge/amd/sb700/Kconfig19
-rw-r--r--src/southbridge/amd/sb700/early_setup.c8
-rw-r--r--src/southbridge/amd/sb700/lpc.c2
-rw-r--r--src/southbridge/amd/sb700/sata.c5
-rw-r--r--src/southbridge/amd/sb700/sb700.c4
-rw-r--r--src/southbridge/amd/sp5100/chip.h33
9 files changed, 24 insertions, 56 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
index cbd3119544..844763e211 100755
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig
@@ -8,14 +8,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_SR5650
- select SOUTHBRIDGE_AMD_SP5100
+ select SOUTHBRIDGE_AMD_SB700
+ select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
select SUPERIO_WINBOND_W83627HF
select SUPERIO_NUVOTON_WPCM450
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
- select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
index c6ccecb171..9aa4406faf 100644
--- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
@@ -36,7 +36,7 @@ chip northbridge/amd/amdfam10/root_complex
register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
register "port_enable" = "0x1ffc"
end
- chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pri bus
+ chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
@@ -92,7 +92,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # USB 2
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/sp5100
+ end #southbridge/amd/sb700
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 54245f2543..65e4729b14 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 05f7d099cc..924e2df761 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -19,29 +19,34 @@
config SOUTHBRIDGE_AMD_SB700
bool
+
+if SOUTHBRIDGE_AMD_SB700
+
+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
+ def_bool y
select IOAPIC
select HAVE_USBDEBUG
select HAVE_HARD_RESET
-config SOUTHBRIDGE_AMD_SP5100
+# Set for southbridge SP5100 which also uses SB700 driver
+config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool
- select IOAPIC
- select HAVE_USBDEBUG
+ default n
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/sb700/bootblock.c"
- depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
bool
default n
- depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
config EHCI_BAR
hex
- default 0xfef00000 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
+ default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
- default 0xe0 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
+ default 0xe0
+
+endif # SOUTHBRIDGE_AMD_SB700
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 1f46da2228..2dc84d84bc 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -154,7 +154,7 @@ void sb7xx_51xx_lpc_init(void)
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
post_code(0x66);
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
reg8 = pci_read_config8(dev, 0xBB);
@@ -168,7 +168,7 @@ void sb7xx_51xx_lpc_init(void)
// XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if CONFIG_TTYS0_BASE == 0x2f8
reg8 |= 1 << 7;
#endif
@@ -358,7 +358,7 @@ static void sb700_devices_por_init(void)
{
device_t dev;
u8 byte;
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
u32 dword;
#endif
@@ -494,7 +494,7 @@ static void sb700_devices_por_init(void)
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
pci_write_config8(dev, 0x50, 0x01);
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
/* SP5100 default SATA mode is RAID5 MODE */
dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
/* Set SATA Operation Mode, Set to IDE mode */
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 3e596c240d..5dd7d696aa 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
/* Disable FlowContrl, Always service the request from Host
* whenever there is a request from Host pending
*/
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 58b72ad538..bdbb08a645 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -86,9 +86,6 @@ static void sata_init(struct device *dev)
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
- struct southbridge_ati_sb700_config *conf;
- conf = dev->chip_info;
-
device_t sm_dev;
/* SATA SMBus Disable */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -189,7 +186,7 @@ static void sata_init(struct device *dev)
byte |= 7 << 0;
pci_write_config8(dev, 0x4, byte);
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
/* Master Latency Timer */
pci_write_config32(dev, 0xC, 0x00004000);
#endif
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index 845c82cf54..304bd07399 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -226,8 +226,8 @@ void sb7xx_51xx_enable(device_t dev)
}
}
-#if CONFIG_SOUTHBRIDGE_AMD_SP5100
-struct chip_operations southbridge_amd_sp5100_ops = {
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+struct chip_operations southbridge_amd_sb700_ops = {
CHIP_NAME("ATI SP5100")
.enable_dev = sb7xx_51xx_enable,
};
diff --git a/src/southbridge/amd/sp5100/chip.h b/src/southbridge/amd/sp5100/chip.h
deleted file mode 100644
index 569e511108..0000000000
--- a/src/southbridge/amd/sp5100/chip.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef SP5100_CHIP_H
-#define SP5100_CHIP_H
-
-struct southbridge_amd_sp5100_config
-{
- u32 ide0_enable : 1;
- u32 sata0_enable : 1;
- u32 boot_switch_sata_ide : 1;
- u32 hda_viddid;
-};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sp5100_ops;
-
-#endif /* SP5100_CHIP_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 09:50:38 +0000